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LP8550TLE/NOPB.A 数据表(PDF) 26 Page - Texas Instruments |
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LP8550TLE/NOPB.A 数据表(HTML) 26 Page - Texas Instruments |
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26 / 49 page ![]() EEPROM NVM 8 x 8 bits REGISTERS ADDRESS 00h...72h Startup or EE_READ=1 User Device Control EEPROM REGISTERS Address A0h...A7h EE_PROG = 1 Device Control LP8550 SNVS657E – SEPTEMBER 2010 – REVISED SEPTEMBER 2014 www.ti.com Figure 26. EEPROM Control Structure 8.6 Register Maps Table 6. Register Map ADDR REGISTER D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT 00H Brightness Control BRT[7:0] 0000 0000 01H Device Control BRT_MODE[1:0] BL_CTL 0000 0000 02H Fault OPEN SHORT 2_CHANNELS 1_CHANNEL BL_FAULT OCP TSD UVLO 0000 0000 03H ID PANEL MFG[3:0] REV[2:0] 1111 1100 04H Direct Control OUT[6:1] 0000 0000 05H Temp MSB TEMP[10:3] 0000 0000 06H Temp LSB TEMP[2:0] 0000 0000 72H EEPROM_control EE_READY EE_INIT EE_PROG EE_READ 0000 0000 8.6.1 Register Bit Explanations 8.6.1.1 Brightness Control Address 00h Reset value 0000 0000b BRIGHTNESS CONTROL REGISTER 7 6 5 4 3 2 1 0 BRT[7:0] Name Bit Access Description BRT 7:0 R/W Backlight PWM 8-bit linear control. 8.6.1.2 Device Control Address 01h Reset value 0000 0000b DEVICE CONTROL REGISTER 7 6 5 4 3 2 1 0 BRT_MODE[1:0] BL_CTL Name Bit Access Description 26 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: LP8550 |
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