Symbol

Parameters

Test conditions

Min.

Typ.

Max

Unit

VOL(1)

Output low voltage

Isink = 1 mA

0.4

V

IOZH, IOZL

Hi-impedance output

leakage current

-1

1

µA

COUT

Hi-impedance output

capacitance

4.5

pF

Power supply characteristic

IAVCC + IDVCC

Total supply current, normal

mode (CS low)

AVCC = DVCC = +2.7 V to

+3.6 V, fS = 1 MSPS,

FIN = 40 kHz

2

mA

Total supply current,

shutdown mode (CS high)

AVCC = DVCC = +2.7 V to

+3.6 V, fS = 0

5

µA

AC characteristics (AVCC = DVCC = +2.7 V to +3.6 V)

tCONVERT

Conversion (Hold) time

13

SCLK

cycles

DC

SCLK duty cycle

40

60

%

tACQ

Acquisition (Track) Time

cycles

See figure 3

3

SCLK

cycles

Throughput time Acquisition

time + Conversion time

16

SCLK

cycles

tAD

Aperture delay

4

ns

Timing specifications (AVCC = DVCC = +2.7 V to +3.6 V) (2)

tCSH

CS/ hold time after SCLK

rising edge

(3)

10

0

ns

tCSS

CS/ setup time prior SCLK

rising edge

(3)

10

4.5

ns

tEN

CS/falling edge to DOUT

enabled

5

30

ns

tDACC

DOUT access time after

SCLK falling edge

Load 25 pF

17

27

ns

tDHLD

DOUT hold time after SCLK

falling edge

7

4

ns

tDS

DIN setup time prior to

SCLK rising edge

10

ns

tDH

DIN hold time after SCLK

rising edge

10

ns

tDIS

CS/ rising edge to DOUT

high-impedance

DOUT falling

2.4

20

ns

DOUT rising

0.9

20

tCH

Min. SCLK high time

0.4 x tSCLK

ns

tCL

Min. SCLK low time

0.4 x tSCLK

ns

1. Limits are guaranteed by functional test.

2. Limits are guaranteed by design or characterization.

3. Clock may be in any state (high or low) when CS/ goes high. Setup and hold time restrictions apply only to CS/ going low.

ADC120

Electrical characteristics

DS12987 - Rev 1

page 6/15