1

Functional description

Figure 1. Pin description (top view)

IN1

IN2

DGND

DVCC

IN6

IN5

AGND

AVCC

11

14

13

12

8

10

9

1

2

3

4

5

6

7

IN0

IN7

DIN

IN3

IN4

/CS

DOUT

16

15

SCLK

Figure 2. Block diagram

IN0

IN7

Input

Mux.

T/H

AGND

12 bit

SAR

ADC

AGND

AVCC

DVCC

DGND

/CS

SCLK

DIN

DOUT

Control

Logic

Table 1. Control register bits

Bit#

7 (MSB)

6

5

4

3

2

1

0

Symbol

Any code except 11

ADD2

ADD1

ADD0

Any code except 001

Table 2. Control register bit description

Bit#

Symbol

Description

7, 6, 2, 1, 0

DONTC

Don’t care (forbidden codes provided in Table 1. Control register bits)

5

ADD2

They determine which input channel converted, as per Table 3. Input channel

description.

4

ADD1

3

ADD0

ADC120

Functional description

DS12987 - Rev 1

page 2/15