7.17 I2C I/O (continued)

Unless otherwise noted, characteristics noted under conditions of TA = –40℃ to 85℃

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CI

Input capacitance

10

pF

Ilkg

Input leakage current

1

µA

7.18 I2C Timing — 100 kHz

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

fSCL

Clock operating frequency

SCL duty cycle = 50%

100

kHz

tHD:STA

Start condition hold time

4.0

µs

tLOW

Low period of the SCL Clock

4.7

µs

tHIGH

High period of the SCL Clock

4.0

µs

tSU:STA

Setup repeated START

4.7

µs

tHD:DAT

Data hold time (SDA input)

0

ns

tSU:DAT

Data setup time (SDA input)

250

ns

tr

Clock rise time

10% to 90%

1000

ns

tf

Clock fall time

90% to 10%

300

ns

tSU:STO

Setup time STOP condition

4.0

µs

tBUF

Bus free time STOP to

START

4.7

µs

7.19 I2C Timing — 400 kHz

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

fSCL

Clock operating frequency

SCL duty cycle = 50%

400

kHz

tHD:STA

START condition hold time

0.6

µs

tLOW

Low period of the SCL Clock

1.3

µs

tHIGH

High period of the SCL Clock

600

ns

tSU:STA

Setup repeated START

600

ns

tHD:DAT

Data hold time (SDA input)

0

ns

tSU:DAT

Data setup time (SDA input)

100

ns

tr

Clock rise time

10% to 90%

300

ns

tf

Clock fall time

90% to 10%

300

ns

tSU:STO

Setup time STOP condition

0.6

µs

tBUF

Bus free time STOP to

START

1.3

µs

7.20 HDQ Timing

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

tB

Break time

190

µs

tBR

Break recovery time

40

µs

tHW1

Host write 1 time

Host drives HDQ

0.5

50

µs

tHW0

Host write 0 time

Host drives HDQ

86

145

µs

tCYCH

Cycle time, host to device

Device drives HDQ

190

µs

tCYCD

Cycle time, device to Host

Device drives HDQ

190

205

250

µs

tDW1

Device write 1 time

Device drives HDQ

32

50

µs

tDW0

Device write 0 time

Device drives HDQ

80

145

µs

tRSPS

Device response time

Device drives HDQ

190

950

µs

BQ27Z561-R1

SLUSDH5B – MARCH 2019 – REVISED DECEMBER 2022

www.ti.com

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