for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the

CD74HCT03, as specified in the Section 6.4, and the desired input transition rate. A 10-kΩ resistor value is often

used due to these factors.

Refer to the Section 8.3 for additional information regarding the inputs for this device.

9.2.1.3 Output Considerations

The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the

output voltage as specified by the VOL specification in the Section 6.4. The plot in provides a typical relationship

between output voltage and current for this device.

Open-drain outputs can be directly connected together to produce a wired-AND. This is possible because the

outputs cannot source current, and thus can never be in bus-contention.

Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.

Refer to Section 8.3 for additional information regarding the outputs for this device.

9.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Section 11.

2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal

performance. This can be accomplished by providing short, appropriately sized traces from the CD74HCT03

to the receiving device.

3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum

output current from the Section 6.1 is not violated. Most CMOS inputs have a resistive load measured in

megaohms; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation

9.2.3 Application Curves

PG 2

Output

PG 1

Figure 9-2. Typical application timing diagram

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CD74HCT03, CD54HCT03

SCHS414 – JUNE 2020

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