CDCE925PWR datasheet(21/40 Pages) TI2

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CDCE925, CDCEL925

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SCAS847I – JULY 2007 – REVISED OCTOBER 2016

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Table 10. PLL1 Configuration Register (continued)

OFFSET(1)

BIT(2)

ACRONYM

DEFAULT(3)

DESCRIPTION

(5)

PLL settings limits: 16

≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096

13h

FS1_7

FS1_x: PLL1 frequency selection(4)

FS1_6

0 – fVCO1_0 (predefined by PLL1_0 – multiplier/divider value)

1 – fVCO1_1 (predefined by PLL1_1 – multiplier/divider value)

FS1_5

FS1_4

FS1_3

FS1_2

FS1_1

FS1_0

14h

MUX1

PLL1 multiplexer:

0 – PLL1

1 – PLL1 bypass (PLL1 is in power down)

Output Y2 multiplexer: 0 – Pdiv1

1 – Pdiv2

5:4

10b

Output Y3 multiplexer: 00 – Pdiv1-divider

01 – Pdiv2-divider

10 – Pdiv3-divider

11 – Reserved

3:2

Y2Y3_ST1

11b

Y2, Y3-

state0/1definition:

00 – Y2/Y3 disabled to high-impedance state (PLL1 is in power

down)

01 – Y2/Y3 disabled to high-impedance state (PLL1 on)

10 – Y2/Y3 disabled to low (PLL1 on)

11 – Y2/Y3 enabled (normal operation, PLL1 on)

1:0

Y2Y3_ST0

01b

15h

Y2Y3_7

Y2Y3_x output state selection(4)

Y2Y3_6

0 – state0 (predefined by Y2Y3_ST0)

1 – state1 (predefined by Y2Y3_ST1)

Y2Y3_5

Y2Y3_4

Y2Y3_3

Y2Y3_2

Y2Y3_1

Y2Y3_0

16h

SSC1DC

PLL1 SSC down/center selection: 0 – Down

1 – Center

6:0

Pdiv2

01h

7-bit Y2-output-divider Pdiv2:

0 – Reset and in standby

1 to 127 – Divider value

17h

—

Reserved – do not write others than 0

6:0

Pdiv3

01h

7-bit Y3-output-divider Pdiv3:

0 – Reset and in standby

1 to 127 – Divider value

18h

7:0

PLL1_0N [11:4

004h

PLL1_0(5): 30-bit multiplier/divider value for frequency fVCO1_0

(for more information, see PLL Multiplier/Divider Definition).

19h

7:4

PLL1_0N [3:0]

3:0

PLL1_0R [8:5]

000h

1Ah

7:3

PLL1_0R[4:0]

2:0

PLL1_0Q [5:3]

10h

1Bh

7:5

PLL1_0Q [2:0]

4:2

PLL1_0P [2:0]

010b

1:0

VCO1_0_RANGE

00b

fVCO1_0 range selection:

00 – fVCO1_0 < 125 MHz

01 – 125 MHz

≤ fVCO1_0 < 150 MHz

10 – 150 MHz

≤ fVCO1_0 < 175 MHz

11 – fVCO1_0 ≥ 175 MHz

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