EEPROM

Xin/CLK

Xout

VDD

GND

Vctr

VDDOUT

VCXO

XO

LVCMOS

Y2

Y1

Y3

LV

CMOS

Pdiv1

10-Bit

Y4

Y5

LV

CMOS

Pdiv5

7-Bit

Pdiv4

7-Bit

LV

CMOS

LV

CMOS

Pdiv3

7-Bit

Pdiv2

7-Bit

LV

CMOS

Programming

and

SDA/SCL

Register

Input Clock

PLL Bypass

PLL 1

With SSC

PLL Bypass

PLL 2

With SSC

S0

S1/SDA

S2/SCL

Copyright © 2016, Texas Instruments Incorporated

13

CDCE925, CDCEL925

www.ti.com

SCAS847I – JULY 2007 – REVISED OCTOBER 2016

Product Folder Links: CDCE925 CDCEL925

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Copyright © 2007–2016, Texas Instruments Incorporated

9.2 Functional Block Diagram

Figure 6. Functional Block Diagram for CDCEx925

9.3 Feature Description

9.3.1 Control Terminal Setting

The CDCEx925 has three user-definable control terminals (S0, S1, and S2) which allow external control of

device settings. They can be programmed to any of the following settings:

•

Spread spectrum clocking selection

→ spread type and spread amount selection

•

Frequency selection

→ switching between any of two user-defined frequencies

•

Output state selection

→ output configuration and power-down control

The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.

Table 1. Control Terminal Definition

EXTERNAL

CONTROL

BITS

PLL1 SETTING

PLL2 SETTING

Y1 SETTING

Control

function

PLL frequency

selection

SSC

selection

Output Y2/Y3

selection

PLL frequency

selection

SSC

selection

Output Y4/Y5

selection

Output Y1 and power-

down selection

(1)

Center/down-spread, Frequency0/1 and State0/1 are user-definable in the PLLx configuration register.

Table 2. PLL Setting (Can Be Selected for Each PLL Individual)(1)

SSC SELECTION (CENTER/DOWN)

SSCx [3-Bits]

CENTER

DOWN

0

0

0

0% (off)

0% (off)

0

0

1

±0.25%

–0.25%

0

1

0

±0.5%

–0.5%

0

1

1

±0.75%

–0.75%

1

0

0

±1%

–1.0%

1

0

1

±1.25%

–1.25%