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CDCE925, CDCEL925

SCAS847I – JULY 2007 – REVISED OCTOBER 2016

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Table 10. PLL1 Configuration Register (continued)

OFFSET(1)

BIT(2)

ACRONYM

DEFAULT(3)

DESCRIPTION

1Ch

7:0

PLL1_1N [11:4]

004h

PLL1_1(5): 30-bit multiplier/divider value for frequency fVCO1_1

(for more information, see PLL Multiplier/Divider Definition).

1Dh

7:4

PLL1_1N [3:0]

3:0

PLL1_1R [8:5]

000h

1Eh

7:3

PLL1_1R[4:0]

2:0

PLL1_1Q [5:3]

10h

1Fh

7:5

PLL1_1Q [2:0]

4:2

PLL1_1P [2:0]

010b

1:0

VCO1_1_RANGE

00b

fVCO1_1 range selection:

00 – fVCO1_1 < 125 MHz

01 – 125 MHz

≤ fVCO1_1 < 150 MHz

10 – 150 MHz

≤ fVCO1_1 < 175 MHz

11 – fVCO1_1 ≥ 175 MHz

(1)

Writing data beyond 30h may adversely affect device function.

(2)

All data is transferred MSB-first.

(3)

Unless a custom setting is used

(4)

The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external

control pins, S0, S1, and S2.

Table 11. PLL2 Configuration Register

OFFSET(1)

BIT(2)

ACRONYM

DEFAULT(3)

DESCRIPTION

20h

7:5

SSC2_7 [2:0]

000b

SSC2: PLL2 SSC selection (modulation amount). (4)

4:2

SSC2_6 [2:0]

000b

Down

000 (Off)

001 – 0.25%

010 – 0.5%

011 – 0.75%

100 – 1.0%

101 – 1.25%

110 – 1.5%

111 – 2.0%

Center

000 (Off)

001 ± 0.25%

010 ± 0.5%

011 ± 0.75%

100 ± 1.0%

101 ± 1.25%

110 ± 1.5%

111 ± 2.0%

1:0

SSC2_5 [2:1]

000b

21h

7

SSC2_5 [0]

6:4

SSC2_4 [2:0]

000b

3:1

SSC2_3 [2:0]

000b

0

SSC2_2 [2]

000b

22h

7:6

SSC2_2 [1:0]

5:3

SSC2_1 [2:0]

000b

2:0

SSC2_0 [2:0]

000b

23h

7

FS2_7

0b

FS2_x: PLL2 frequency selection(4)

6

FS2_6

0b

0 – fVCO2_0 (predefined by PLL2_0 – multiplier/divider value)

1 – fVCO2_1 (predefined by PLL2_1 – multiplier/divider value)

5

FS2_5

0b

4

FS2_4

0b

3

FS2_3

0b

2

FS2_2

0b

1

FS2_1

0b

0

FS2_0

0b

24h

7

MUX2

1b

PLL2 multiplexer:

0 – PLL2

1 – PLL2 bypass (PLL2 is in power down)

6

M4

1b

Output Y4

multiplexer:

0 – Pdiv2

1 – Pdiv4

5:4

M5

10b

Output Y5

multiplexer:

00 – Pdiv2-divider

01 – Pdiv4-divider

10 – Pdiv5-divider

11 – Reserved

3:2

Y4Y5_ST1

11b

Y4, Y5-

State0/1definition:

00 – Y4/Y5 disabled to high-impedance state (PLL2 is in power

down)

01 – Y4/Y5 disabled to high-impedance state (PLL2 on)

10–Y4/Y5 disabled to low (PLL2 on)

11 – Y4/Y5 enabled (normal operation, PLL2 on)

1:0

Y4Y5_ST0

01b