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CDCE925, CDCEL925

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SCAS847I – JULY 2007 – REVISED OCTOBER 2016

Product Folder Links: CDCE925 CDCEL925

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Copyright © 2007–2016, Texas Instruments Incorporated

Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

(2)

10,000 cycles

(3)

Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 135 MHz, fOUT = 27 MHz. fOUT = 3.072 MHz or input

frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz. fOUT = 16.384 MHz, fOUT = 25 MHz, fOUT = 74.25 MHz, fOUT = 48 MHz

(4)

The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider,

data sampled on rising edge (tr).

(5)

odc depends on output rise- and fall-time (tr/tf);

CI

Input capacitance at Xin/Clk

VIClk = 0 V or VDD

6

pF

Input capacitance at Xout

VIXout = 0 V or VDD

2

Input capacitance at S0/S1/S2

VIS = 0 V or VDD

3

CDCE925 – LVCMOS FOR VDDOUT = 3.3 V

VOH

LVCMOS high-level output voltage

VDDOUT = 3 V, IOH = –0.1 mA

2.9

V

VDDOUT = 3 V, IOH = –8 mA

2.4

VDDOUT = 3 V, IOH = –12 mA

2.2

VOL

LVCMOS low-level output voltage

VDDOUT = 3 V, IOL = 0.1 mA

0.1

V

VDDOUT = 3 V, IOL = 8 mA

0.5

VDDOUT = 3 V, IOL = 12 mA

0.8

tPLH, tPHL

Propagation delay

All PLL bypass

3.2

ns

tr/tf

Rise and fall time

VDDOUT = 3.3 V (20%–80%)

0.6

ns

tjit(cc)

Cycle-to-cycle jitter(2)(3)

1 PLL switching, Y2-to-Y3

50

70

ps

2 PLL switching, Y2-to-Y5

90

130

tjit(per)

Peak-to-peak period jitter(3)

1 PLL switching, Y2-to-Y3

60

100

ps

2 PLL switching, Y2-to-Y5

100

160

tsk(o)

Output skew (4)

fOUT = 50 MHz, Y1-to-Y3

70

ps

fOUT = 50 MHz, Y2-to-Y5

150

odc

Output duty cycle (5)

fVCO = 100 MHz, Pdiv = 1

45%

55%

CDCE925 – LVCMOS FOR VDDOUT = 2.5 V

VOH

LVCMOS high-level output voltage

VDDOUT = 2.3 V, IOH = –0.1 mA

2.2

V

VDDOUT = 2.3 V, IOH = –6 mA

1.7

VDDOUT = 2.3 V, IOH = –10 mA

1.6

VOL

LVCMOS low-level output voltage

VDDOUT = 2.3 V, IOL = 0.1 mA

0.1

V

VDDOUT = 2.3 V, IOL = 6 mA

0.5

VDDOUT = 2.3 V, IOL = 10 mA

0.7

tPLH, tPHL

Propagation delay

All PLL bypass

3.6

ns

tr/tf

Rise and fall time

VDDOUT = 2.5 V (20%–80%)

0.8

ns

tjit(cc)

Cycle-to-cycle jitter(2) (3)

1 PLL switching, Y2-to-Y3

50

70

ps

2 PLL switching, Y2-to-Y5

90

130

tjit(per)

Peak-to-peak period jitter(3)

1 PLL switching, Y2-to-Y3

60

100

ps

2 PLL switching, Y2-to-Y5

100

160

tsk(o)

Output skew(4)

fOUT = 50 MHz, Y1-to-Y3

70

ps

fOUT = 50 MHz, Y2-to-Y5

150

odc

Output duty cycle(5)

fVCO = 100 MHz, Pdiv = 1

45%

55%

CDCEL925 – LVCMOS FOR VDDOUT = 1.8 V

VOH

LVCMOS high-level output voltage

VDDOUT = 1.7 V, IOH = –0.1 mA

1.6

V

VDDOUT = 1.7 V, IOH = –4 mA

1.4

VDDOUT = 1.7 V, IOH = –8 mA

1.1

VOL

LVCMOS low-level output voltage

VDDOUT = 1.7 V, IOL = 0.1 mA

0.1

V

VDDOUT = 1.7 V, IOL = 4 mA

0.3

VDDOUT = 1.7 V, IOL = 8 mA

0.6

tPLH, tPHL

Propagation delay

All PLL bypass

2.6

ns

tr/tf

Rise and fall time

VDDOUT = 1.8 V (20%–80%)

0.7

ns