STM32F446MC datasheet(36/202 Pages) STMICROELECTRONICS

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Functional overview

STM32F446xC/E

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DocID027107 Rev 6

The SPDIF-RX also offers a signal named spdifrx_frame_sync, which toggles at the S/PDIF

sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.

3.28

Serial Audio interface (SAI)

The devices feature two serial audio interfaces (SAI1 and SAI2). Each serial audio

interfaces based on two independent audio sub blocks which can operate as transmitter or

receiver with their FIFO. Many audio protocols are supported by each block: I2S standards,

LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling

frequencies from 8 kHz up to 192 kHz. Both sub blocks can be configured in master or in

slave mode. The SAIs use a PLL to achieve audio class accuracy.

In master mode, the master clock can be output to the external DAC/CODEC at 256 times of

the sampling frequency.

The two sub blocks can be configured in synchronous mode when full-duplex mode is

required.

SAI1 and SA2 can be served by the DMA controller.

3.29

Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows

to achieve error-free I2S sampling clock accuracy without compromising on the CPU

performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change

without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging

from 8 KHz to 192 KHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the

I2S/SAI flow with an external PLL (or Codec output).

3.30

Serial Audio Interface PLL(PLLSAI)

An additional PLL dedicated to audio and USB is used for SAI1 and SAI2 peripheral in case

the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or

11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.

The PLLSAI is also used to generate the 48MHz clock for USB FS and SDIO in case the

system PLL is programmed with factors not multiple of 48MHz.

3.31

Secure digital input/output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory

Card Specification Version 2.0.

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