7.3 Layout

7.3.1 Layout Guidelines

Voltage clearance on the line must be respected. A minimum of two layers is required for the ISOTMP35R

device. Standard layer stacking can be used for a 4-layer PCB where the signal traces can run either on the

top or bottom layer. Solid ground and power plane must form the inner layer. See Figure 7-5 for a depiction of a

plane and trace clearance under the device.

Keep this space free

from planes, traces,

pads and vias

10 mils

Figure 7-5. PCB Cross-Section

7.3.2 Layout Example

Keep space beneath

device free of any planes,

traces, pads and vias

VDD

VOUT

GND

NC

NC

NC

ISOTMP35R

1

2

4

5

6

7

8

9

10

11

12

Heat

High Voltage Heat Source

To ADC Input

To GND Plane

To VDD Plane

Bypass

Capacitor

Filter

Capacitor

Filter Resistor

Load

Capacitor

To GND Plane

3

Figure 7-6. ISOTMP35R Layout Example

8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed below.

ISOTMP35R

SNIS244 – SEPTEMBER 2025

www.ti.com

16

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Product Folder Links: ISOTMP35R