5.5 Insulation Specification

Over free-air temperature range and VDD = 3V to 34V (unless otherwise noted)

Typical specifications are at TA = 25°C and VDD = 3.3V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VALUE

UNIT

GENERAL

CLR

External Clearance(1)

Shortest terminal-to-terminal distance through air

>8

mm

CPG

External Creepage(1)

Shortest terminal-to-terminal distance across the package surface

>8

mm

DTI

Distance through the insulation Minimum internal gap (internal clearance)

17

µm

CTI

Comparative tracking index

DIN EN 60112; IEC 60112

>600

V

VDC

Maximum isolation DC voltage DC voltage

1500

VDC

Material Group

According to IEC 60664-1

I

Overvoltage category

Rated mains voltage ≤ 150VRMS

I-IV

Rated mains voltage ≤ 300VRMS

I-III

VIORM

Maximum repetitive peak

isolation voltage

AC voltage (bipolar)

1500

VPK

VIOWM

Maximum isolation working

voltage

AC voltage (sine wave), time-dependent dielectric breakdown

(TDDB) test

1060

VRMS

VIOTM

Maximum transient isolation

voltage

VTEST = VIOTM, t = 60s (qualification test),

VTEST = 1.2 × VIOTM, t = 1s (100% production test)

7000

VPK

VIMP

Maximum impulse voltage(2)

Tested in air, 1.2/50μs waveform per IEC 62368-1(5)

8000

VPK

VIOSM

Maximum surge isolation

voltage(3)

Tested in oil (qualification test),

1.2/50μs waveform per IEC 62368-1(5)

10400

VPK

qpd

Apparent charge(4)

Method a, after input/output safety test subgroups 2 and 3,

Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.2 × VIORM, tm = 10s

≤5

pC

Method a, after environmental tests subgroup 1,

Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.3 × VIORM, tm = 10s

≤5

Method b, at preconditioning (type test) and routine test,

Vpd(ini) = VIOTM, tini = 1s, Vpd(m) = 1.5 × VIORM, tm = 1s

≤5

CIO

Barrier capacitance,

input to output(5)

VIO = 0.1VPP at 100kHz

TBD

pF

RIO

Insulation resistance,

input to output(5)

VIO = 500V at TA = 25°C

>1012

Ω

VIO = 500V at 100°C ≤ TA ≤ 125°C

>1011

VIO = 500V at TA = 150°C

>109

Pollution degree

2

Climatic category

55/125/21

UL 1577

VISO

Withstand isolation voltage

VTEST = VISO, t = 60s (qualification);

VTEST = 1.2 × VISO, t = 1s (100% production)

5000

VRMS

(1)

Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Take care

to maintain the creepage and clearance distance of the board design to make sure that the mounting pads of the isolator on the

printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal in certain cases.

Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.

(2)

Testing is carried out in air to determine the surge immunity of the package.

(3)

Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.

(4)

Apparent charge is electrical discharge caused by a partial discharge (pd).

(5)

All pins on each side of the barrier tied together creating a two-terminal device.

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ISOTMP35R

SNIS244 – SEPTEMBER 2025

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