 2018 Microchip Technology Inc.

DS50002756A-page 9

dsPIC33CK256MP508

FIGURE 3:

INTERNAL OP AMP CONFIGURATION

VREF

IBUS+

Filter,

Feedback

and Bias

Circuit

45

43

Op Amp 2

PIM22 if Enabled by R7

From Shunt

Resistor (IA)

+

–

VREF

IBUS-

OA1

Bypass

Circuit

20

18

Op Amp 1

PIM25 if Enabled by R25

From Shunt

Resistor (IBUS)

+

–

VREF

Filter,

Feedback

and Bias

Circuit

29

28

Op Amp 3

PIM21 if Enabled by R14

From Shunt

Resistor (IB)

+

–

IBUS+

Voltage

Divider

1k

1k

470 pF

1k

1k

1000 pF

470 pF

Filter, Feedback and Bias Circuit for Op Amp 2 and 3

D

C

30k

30k

E

F

B

A

Differential Amplifier Gain

30k



21k





--------------------15

==

Differential-mode f

3dB

–

1

2

 21k



 470pF

2

----------------1000pF

+





--------------------------------------------------------------------------------65kHz



Common-mode f

3dB

–

1

2

 1k

 470pF



--------------------------------------------340kHz



41

16

23

dsPIC33CK256MP508

D

C

D

C

D

C

B

A

B

A

B

A

E

F

E

F

E

F

PIM57 if Enabled by R26

IA+

IB+

IBUS+

DNP

DNP

DNP

DNP

DNP

DNP

DNP

Op Amp 1 Bypass Circuit

D

C

DNP

DNP

E

F

B

A

DNP