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ADS8699IPWR 数据表(PDF) 40 Page - Texas Instruments |
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ADS8699IPWR 数据表(HTML) 40 Page - Texas Instruments |
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40 / 74 page ![]() 7.5 Programming The device features nine configuration registers (as described in the Register Maps section) and supports two types of data transfer operations: data write (the host configures the device), and data read (the host reads data from the device). 7.5.1 Data Transfer Frame A data transfer frame between the device and the host controller begins at the falling edge of the CONVST/CS pin and ends when the device starts conversion at the subsequent rising edge. The host controller can initiate a data transfer frame by bringing the CONVST/CS signal low (as shown in Figure 7-25) after the end of the CONV phase, as described in the CONV State section. Frame F RVS CONVST/CS td_RVS SCLK SDI Valid Command As per output protocol selection. N SCLKs SDO-x Output Data Word Output Shift Register (OSR) D0 D31 D0 D31 0 SCLK Counter N SCLK Counter Input Shift Register (ISR) Command Processor B0 B31 B0 B31 Data Output or OSR Contents Figure 7-25. Data Transfer Frame ADS8691, ADS8695, ADS8699 SBAS777B – DECEMBER 2016 – REVISED MARCH 2021 www.ti.com 40 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: ADS8691 ADS8695 ADS8699 |
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