TSC2012 datasheet(35/50 Pages) STMICROELECTRONICS

35 / 50 page

5.9

Power supply recommendation

In order to decouple correctly the TSC2011, a 100 nF bypass capacitor can be placed between Vcc and Gnd. This

capacitor must be placed as closer as possible to the supply pins. The figure below shows a start-up time with a

decoupling capacitance of 100 nF.

Figure 71. Start-up time with a decoupling capacitance of 100 nF

-200µ

200µ

400µ

600µ

800µ

-3

-2

-1

Vcc

Vref=0V

Vsense=20mV,

Vcc=5V, Vicm=12V,

RI=10k

Ω

, Cl=10pF connected to Vcc-,

T=25°C

Vout

Time (s)

Vref pin is used to fix the output common mode voltage and it is driven by a low impedance voltage source and

can be decoupled thanks to a 10 nF bypass capacitor.

A greater bypass capacitor added on Vcc pin and Vref pin helps to enhance CMRR and PSRR performance.

5.10

PCB layout recommendations

The layout of the PCB tracks connected to the current sensing, load and power supply is very important. It is a

good practice to use short and wide PCB traces to minimize voltage drops and parasitic inductance.

When a shunt resistance, lower than 1 Ω, is used, a 4-wire connection technique should be used to sense the

current as described in the schematic below. This technique separates pairs of current carrying and voltage-

sensing electrodes to make more accurate measurements by eliminating the lead and contact resistance from the

measurement.

The track connected to the input pin of the TSC2011 has to be considered as a differential pair, it must have the

same length and width, and ideally placed on the same PCB plane, and above all must be routed as far as

possible from noisy source. As this track carries the input bias current, in a range of hundreds of µA, it can be

designed small but always by taking care of its resistivity. Any via in these input tracks are non-recommended to

avoid any parasitic resistance in this path.

To minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top

layer ground planes together in many locations is often used.

A ground plane generally helps to reduce EMI, that is why a multilayer PCB use is suggested as well as the

ground planes as a shield to protect the internal track. In this case, the digital from the analog ground must be

separated and any ground loop must be avoided. Loop area or antenna must be reduced to minimize EMI impact.

The Figure 72. Recommended layout suggests a possible routing for the TSC2011, in order to minimum parasitic

effect.

TSC2010, TSC2011, TSC2012

Application information

DS13057 - Rev 7

page 35/50

TSC2012 数据表(PDF) 35 Page - STMicroelectronics

TSC2012 数据表(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

数据表下载