TSC2012IDT datasheet(49/50 Pages) STMICROELECTRONICS

49 / 50 page

Figure 51.

ON/OFF delay for shutdown mode ..................................................... 22

Figure 52.

Output voltage vs. Vsense beyond the sense operating ....................................... 22

Figure 53.

Power up time delay ............................................................... 22

Figure 54.

Power supply when Vicm > Vcc ........................................................ 23

Figure 55.

Input bias current vs. common mode voltage Vcc = 5 V ....................................... 24

Figure 56.

Power supply when Vicm < Gnd ....................................................... 24

Figure 57.

Vref powered by an external voltage source ............................................... 25

Figure 58.

Output reference to ground .......................................................... 26

Figure 59.

Output reference to Vcc ............................................................. 26

Figure 60.

Split supply ..................................................................... 27

Figure 61.

External supply................................................................... 27

Figure 62.

Schematic for Vocm error ............................................................ 29

Figure 63.

Input current..................................................................... 30

Figure 64.

SHDN pin ...................................................................... 32

Figure 65.

Capacitive load response at Vcc = 3.3 V.................................................. 32

Figure 66.

Capacitive load response at Vcc = 3.3 V with a step of 100 mV .................................. 33

Figure 67.

RC filter when driving ADC........................................................... 33

Figure 68.

Capacitive load response at Vcc = 3.3 V with 720 kHz RC filter .................................. 34

Figure 69.

Capacitive load response at Vcc = 3.3 V with 194 kHz RC filter .................................. 34

Figure 70.

Stability criteria with a serial resistor at VCC = 5 V ........................................... 34

Figure 71.

Start-up time with a decoupling capacitance of 100 nF........................................ 35

Figure 72.

Recommended layout .............................................................. 36

Figure 73.

EMIRR on pin+ ................................................................... 36

Figure 74.

EMIRR on pin- ................................................................... 36

Figure 75.

EMIRR on pin+ (TSC2010) .......................................................... 37

Figure 76.

EMIRR on pin- (TSC2010) ........................................................... 37

Figure 77.

Negative overvoltage recovery VCC = ± 2.5 V .............................................. 38

Figure 78.

Positive overvoltage recovery VCC = ± 2.5 V............................................... 38

Figure 79.

H-Bridge application ............................................................... 39

Figure 80.

TSC2011 H-Bridge application ........................................................ 40

Figure 81.

Solenoid valve application ........................................................... 40

Figure 82.

SO8 package outline ............................................................... 42

Figure 83.

MiniSO8 package outline ............................................................ 43

TSC2010, TSC2011, TSC2012

List of figures

DS13057 - Rev 7

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