TSC2012IDT datasheet(32/50 Pages) STMICROELECTRONICS

32 / 50 page

Figure 64. SHDN pin

•

With GND applied to SHDN pin the TSC2011 is in active mode

•

With Vcc applied to SHDN pin the TSC2011 is in shutdown mode

5.8

Stability

•

Driving switched capacitive loads

Some ADCs get their signal thanks to a sample and hold capacitor. If before a sampling this capacitance is fully

discharged, a fast current load can appear on the output of the TSC2011 during the sampling phase.

The scope probe in the figure below shows the output voltage of the TSC2011 excited by a 40 pF capacitor with a

3.3 Vpp signal at 50 kHz to simulate the sample and hold circuit of the ADC120.

Figure 65. Capacitive load response at Vcc = 3.3 V

-4µ

4µ

8µ

12µ

-8

-7

-6

-5

-4

-3

-2

-1

-1000

-900

-800

-700

-600

-500

-400

-300

-200

-100

100

200

300

400

500

600

700

800

900

1000

Time (s)

Sample and hold

Vout

Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp

T=25°C,

50kHz square signal of 3.3V amplitude

injected in the output through 40pF

The ADC120 has a conversion rate of 50 ksps, which is perfect to sample and hold the output of the TSC2011

without any error.

The graph shows the behavior of the output of the TSC2011 under the worst case condition, as for example,

when there is an ADC120 channel change between two measurements.

If a single channel is used, for sure the change on the sample and hold capacitance are very small, and so the

recovery time is extremely low as described by the figure below.

TSC2010, TSC2011, TSC2012

Application information

DS13057 - Rev 7

page 32/50

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