7.2.2.3 Differential to Single-Ended Output Conversion

Figure 7-3 shows an example of a TLV6001 based signal conversion and filter circuit for systems using single-

ended-input ADCs to convert the analog output voltage into digital. With R1 = R2 = R3 = R4, the output voltage

equals (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement of the

system. For most applications, R1 = R2 = R3 = R4 = 3.3 kΩ and C1 = C2 = 330 pF yields good performance.

DCDC_OUT

DCDC_HGND

HLDO_IN

HLDO_OUT

HGND

INP

INN

NC

AMC3301

DCDC_IN

LDO_OUT

VDD

OUTP

OUTN

GND

DIAG

DCDC_GND

+

±

R4

R3

R1

R2

VREF

ADC

GND

GND

To MCU

C1

C2

GND

TLV6001

Figure 7-3. Connecting the AMC3301 Output to a Single-Ended Input ADC

For more information on the general procedure to design the filtering and driving stages of successive-

approximation-register (SAR) ADCs, see the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest

Distortion and Noise reference guide and 18-Bit Data Acquisition Block (DAQ) Optimized for Lowest Power

reference guide, available for download at www.ti.com.

7.2.3 Application Curve

In frequency inverter applications, the power switches must be protected in case of an overcurrent condition.

To allow for fast powering off of the system, a low delay caused by the isolated amplifier is required. Figure

7-4 shows the typical full-scale step response of the AMC3301. Consider the delay of the required window

comparator and the MCU to calculate the overall response time of the system.

VIN

VOUTP

VOUTN

Figure 7-4. Step Response of the AMC3301

AMC3301

SBAS917C – AUGUST 2019 – REVISED MAY 2025

www.ti.com

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