AMC7832IPAPRG4.B datasheet(26/74 Pages) TI2

26 / 74 page

AMC7832

SLAS836 – MARCH 2014

www.ti.com

8.3.1.2 DAC Register Structure

The DACs input data is written to the individual DAC Data registers (address 0x50 – 0x67) in straight binary

format for all output ranges.

Table 2. DAC Data Format

DAC OUTPUT VOLTAGE (V)

DIGITAL CODE

0 TO +5-V RANGE

0 TO +10-V RANGE

-10 TO 0-V RANGE

0000 0000 0000

–10

0000 0000 0001

0.00122

0.00244

-9.99756

1000 0000 0000

2.5

-5

1111 1111 1110

4.99756

9.99512

-0.00488

1111 1111 1111

4.99878

9.99756

-0.00244

Data written to the DAC Data registers is initially stored in the DAC buffer registers. Transfer of data from the

DAC buffer registers to the active registers is initiated by an update command in the Register Update register

(address 0x0F). Once the active registers are updated, the DAC outputs change to their new values.

The host has the option to read from either the buffer registers or the active registers when accessing the DAC

Data registers. The DAC read back option is configured by the READBACK bit in the Interface Configuration 1

8.3.1.3 DAC Clear Operation

Each DAC can be set to a clear state using either hardware or software. When a DAC goes to clear state it is

loaded with a zero-code input and the output voltage is set according to the operating output range. The DAC

buffer or active registers do not change when the DACs enter the clear state thus allowing the possibility to

return to the same voltage being output before the clear event was issued. Note that the DAC Data registers can

be updated while the DACs are in clear state allowing the DACs to output new values upon return to normal

operation. When the DACs exit the clear state they are immediately loaded with the data in the DAC active

registers and the output is set back to the corresponding level to restore operation.

The DAC Clear registers (address 0xB0 – 0xB1) enable independent control of each DAC clear state through

software. The DACs can also be forced to a clear state through hardware using the ALARMIN terminal. For a

detailed description of this method please refer to the Programmable Out-of-Range Alarms section.

The ALARMIN controlled clear mechanism is a special case of the device capability to force the DACs into clear

state as a response to an alarm event. To enable this functionality the clear-state controlling alarm events must

first be enabled as DAC clear alarm sources in the DAC Clear Source registers (address 0x1A – 0x1B).

Additionally the DAC outputs to be cleared by the selected alarm events need also to be specified in the DAC

Clear Enable registers (address 0x18 – 0x19).

When an alarm event is triggered, the corresponding alarm bit in the Alarm Status registers is set and all the

DACs set to clear in response to this alarm in the DAC Clear Enable registers enter a clear state. Once the alarm

bit is cleared, and as long as no other clear-state controlling alarm events have been triggered, the DACs get re-

loaded with the contents of the DAC active registers and the outputs update accordingly.

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