BQ40Z50-R1 datasheet(3/56 Pages) TI2

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VC4

VC3

VC2

VC1

SRP

SRN

LEDCNTLC

LEDCNTLB

LEDCNTLA

SMBC

PBI

SMBD

DISP

PTC

PTCEN

bq40z50-R1

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SLUSCB3 – JULY 2015

5 Description (continued)

The bq40z50-R1 device supports TURBO BOOST mode by providing the available max power and max current

to the host system. The device also supports Battery Trip Point to send a BTP interrupt signal to the host system

at the pre-set state of charge thresholds.

The bq40z50-R1 provides software-based 1st- and 2nd-level safety protection against overvoltage, undervoltage,

overcurrent, short-circuit current, overload, and overtemperature conditions, as well as other pack- and cell-

related faults.

SHA-1 authentication, with secure memory for authentication keys, enables identification of genuine battery

packs.

The compact 32-lead QFN package minimizes solution cost and size for smart batteries while providing

maximum functionality and safety for battery gauging applications.

6 Pin Configuration and Functions

RSM Package

32-Pin VQFN with Exposed Thermal Pad

Top View

Pin Functions

PIN NAME

NUMBER

TYPE(1)

DESCRIPTION

PBI

Power supply backup input pin

Sense voltage input pin for most positive cell, and balance current input for most positive

VC4

cell

Sense voltage input pin for second most positive cell, balance current input for second

VC3

most positive cell, and return balance current for most positive cell

Sense voltage input pin for third most positive cell, balance current input for third most

VC2

positive cell, and return balance current for second most positive cell

Sense voltage input pin for least positive cell, balance current input for least positive cell,

VC1

and return balance current for third most positive cell

Analog input pin connected to the internal coulomb counter peripheral for integrating a

SRN

small voltage between SRP and SRN where SRP is the top of the sense resistor.

—

Not internally connected. Connect to VSS.

Analog input pin connected to the internal coulomb counter peripheral for integrating a

SRP

small voltage between SRP and SRN where SRP is the top of the sense resistor.

VSS

Device ground

TS1

Temperature sensor 1 thermistor input pin

TS2

Temperature sensor 2 thermistor input pin

TS3

Temperature sensor 3 thermistor input pin

TS4

Temperature sensor 4 thermistor input pin

—

Not internally connected

(1)

P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output

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