BQ40Z50-R1 datasheet(12/56 Pages) TI2

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bq40z50-R1

SLUSCB3 – JULY 2015

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Electrical Characteristics: ADC (continued)

Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Offset error(2)

16-bit, Post-calibration, VFS = VREF1

±67

±157

µV

Offset error drift

16-bit, Post-calibration, VFS = VREF1

0.6

µV/°C

Gain error

16-bit, –0.1 V to 0.8 x VFS

±0.2%

±0.8%

FSR

Gain error drift

16-bit, –0.1 V to 0.8 x VFS

150

PPM/°C

Effective input resistance

(2)

For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and VREF1/2, the offset error is multiplied by (1/ADC

multiplexer scaling factor (K)).

7.17 Electrical Characteristics: ADC Digital Filter

Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Single conversion

31.25

Single conversion

15.63

Conversion time

Single conversion

7.81

Single conversion

1.95

Resolution

No missing codes

Bits

With sign, tCONV = 31.25 ms

With sign, tCONV = 15.63 ms

Effective resolution

Bits

With sign, tCONV = 7.81 ms

With sign, tCONV = 1.95 ms

7.18 Electrical Characteristics: CHG, DSG FET Drive

Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V,

2.133

2.333

2.433

10 M

Ω between PACK and DSG

Output voltage

—

ratio

RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V,

2.133

2.333

2.433

10 M

Ω between BAT and CHG

VDSG(ON) = VDSG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between

10.5

11.5

PACK and DSG, VBAT = 18 V

Output voltage,

V(FETON)

CHG and DSG on V

CHG(ON) = VCHG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between

10.5

11.5

BAT and CHG, VBAT = 18 V

VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and

–0.4

0.4

Output voltage,

DSG

V(FETOFF)

CHG and DSG off

VCHG(OFF) = VCHG – VBAT, 10 MΩ between BAT and CHG

–0.4

0.4

VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2 V, CL =

4.7 nF between DSG and PACK, 5.1 k

Ω between DSG

200

500

and CL, 10 MΩ between PACK and DSG

Rise time

µs

VCHG from 0% to 35% VCHG(ON)(TYP), VBAT ≥ 2.2 V, CL =

4.7 nF between CHG and BAT, 5.1 k

Ω between CHG

200

500

and CL, 10 MΩ between BAT and CHG

VDSG from VDSG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF

between DSG and PACK, 5.1 k

Ω between DSG and CL,

300

10 M

Ω between PACK and DSG

Fall time

µs

VCHG from VCHG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7

nF between CHG and BAT, 5.1 k

Ω between CHG and

200

CL, 10 MΩ between BAT and CHG

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