MB85RS2MLY(AEC-Q100 Compliant)

DS501-00062-3v1-E

9



READ

The READ command reads FeRAM memory cell array data. Arbitrary 24 bits address and op-code of READ

are input to SI. The 6-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output

synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ

command is completed, but keeps on reading with automatic address increment which is enabled by con-

tinuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant

address, it rolls over to the starting address, and reading cycle keeps on infinitely.



WRITE

The WRITE command writes data to FeRAM memory cell array. WRITE op-code, arbitrary 24 bits of address

and 8 bits of writing data are input to SI. The 6-bit upper address bit is invalid. When 8 bits of writing data is

input, data is written to FeRAM memory cell array. Risen CS will terminate the WRITE command, but if you

continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with

automatic address increment. When it reaches the most significant address, it rolls over to the starting

address, and writing cycle can be continued infinitely.



FSTRD

The FSTRD command reads FeRAM memory cell array data. Arbitrary 24 bits address and op-code of

FSTRD are input to SI followed by 8 bits dummy. The 6-bit upper address bit is invalid. Then, 8-cycle clock

is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid.

When CS is risen, the FSTRD command is completed, but keeps on reading with automatic address incre-

ment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it

reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely.

CS

SCK

SI

Invalid

MSB

LSB

MSB

Data Out

LSB

High-Z

Invalid

45

0123

26 27

6 7 8 9 10 11 12 13 14 15

38 39

28 29 30 31 32 33 34 35 36 37

00000011 X

32

XXXXX 17 16

54

SO

76

3

10

54

210

24-bit Address

OP-CODE

CS

SCK

Data In

SI

MSB

24-bit Address

OP-CODE

LSB MSB

LSB

High-Z

10 11

0123456789

14 15

26

31 32

12 13

27 28 29 30

33 34 35 36 37 38 39

0000001

3

0 XXXXX

2 1 0

SO

X17 16

5 4

3 2 1 0

7654

CS

SCK

SI

Invalid

MSB

LSB

MSB

Data Out

LSB

High-Z

Invalid

45

0123

29 30

6 7 8 9 10 11 12 13 1415

46 47

31 32

38 39 40 41 42 43 44 45

00001011 X

6

16

210 X

XX

SO

7

XXXXX 17

0

543

33

X

21

24-bit Address

8-bit Dummy

OP-CODE