MB85RS2MLY(AEC-Q100 Compliant)

2

DS501-00062-3v1-E



PIN ASSIGNMENT



PIN FUNCTIONAL DESCRIPTIONS

Pin No. Pin Name

Functional description

1

CS

Chip Select pin

This is an input pin to make chips select. When CS is “H” level, device is in deselect

(standby) status and SO becomes High-Z. Inputs from other pins are ignored for this

time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before

inputting op-code.

3

WP

Write Protect pin

This is a pin to control writing to a status register. The writing of status register (see “

STATUS REGISTER”) is protected in related with WP and WPEN. See “ WRITING

PROTECT” for detail.

7

NC

NC pin

This pin is not used. No connection or connecting VDD or VCC is allowed.

6

SCK

Serial Clock pin

This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising

edge, SO is output synchronously to a falling edge.

5

SI

Serial Data Input pin

This is an input pin of serial data. This inputs op-code, address, and writing data.

2

SO

Serial Data Output pin

This is an output pin of serial data. Reading data of FeRAM memory cell array and status

register data are output. This is High-Z during standby.

8

VDD

Supply Voltage pin

4

VSS

Ground pin

DIE PAD



It is allowed for the DIE PAD on the bottom of the DFN8 package to be floating (no con-

nection to anything) or to be connected to VSS.

VSS

SI

SO

VDD

SCK

WP

CS

NC

8

7

6

5

4

3

2

1

(8-pin plastic SOP 150mil)

(TOP VIEW)

VSS

SI

SO

VDD

SCK

WP

CS

NC

8

7

6

5

4

3

2

1

DIE PAD

(8-pin plastic DFN 5mm  6mm)

(TOP VIEW)