DAC8563 datasheet(34/63 Pages) TI2

34 / 63 page

DAC7562, DAC7563, DAC8162

DAC8163, DAC8562, DAC8563

SLAS719E – AUGUST 2010 – REVISED JUNE 2015

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8.4.4 Internal Reference Enable Register

The internal reference in the DAC756x, DAC816x, and DAC856x devices is disabled by default for debugging,

evaluation purposes, or when using an external reference. The internal reference can be powered up and

powered down by setting the serial interface command bits to 111 and configuring DB0 (see Table 9). The

internal reference is forced to a powered down state while both DAC channels are powered down, and can only

be enabled if any DAC channel is in normal mode of operation. During the time that the internal reference is

disabled, the DAC functions normally using an external reference. At this point, the internal reference is

disconnected from the VREFIN/VREFOUT pin (Hi-Z output).

Table 9. Internal Reference

DB0

Internal Reference Configuration

Disable internal reference and reset DACs to gain = 1

Enable internal reference and reset DACs to gain = 2

8.4.4.1 Enabling Internal Reference

To enable the internal reference, refer to the command structure in Table 17. When performing a power cycle to

reset the device, the internal reference is switched off (default mode). In the default mode, the internal reference

is powered down until a valid write sequence powers up the internal reference. However, the internal reference is

forced to a disabled state while both DAC channels are powered down, and remains disabled until either DAC

channel is returned to the normal mode of operation. See DAC Power-Down Commands for more information on

DAC channel modes of operation.

8.4.4.2 Disabling Internal Reference

To disable the internal reference, refer to the command structure in Table 17. When performing a power cycle to

reset the device, the internal reference is disabled (default mode).

8.4.5 CLR Functionality

The edge-triggered CLR pin can be used to set the input and DAC registers immediately according to Table 10.

When the CLR pin receives a falling edge signal the clear mode is activated and changes the DAC output

voltages accordingly. The device exits clear mode on the 24th falling edge of the next write to the device. If the

CLR pin receives a falling edge signal during a write sequence in normal operation, the clear mode is activated

and changes the input and DAC registers immediately according to Table 10.

Table 10. Clear Mode Reset Values

DEVICE

DAC Output Entering Clear Mode

DAC8562, DAC8162, DAC7562

Zero-scale

DAC8563, DAC8163, DAC7563

Mid-scale

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