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L9396 数据表(PDF) 84 Page - STMicroelectronics |
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L9396 数据表(HTML) 84 Page - STMicroelectronics |
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84 / 109 page  System functional safety implementations L9396 84/109 DS12539 Rev 10 Figure 23. WD2 diagram 7.4.3 Watchdog Timer Disable Input (WDTDIS) When controlled to a voltage higher than VIH_WDTDIS, this pin is used to disable the WD2 timer. It implements a passive pulldown to ensure the voltage level would not interrupt the WD control in case of open connection. The state of this pin can be read by SPI because it is acquired by an internal A2D converter. When WDTDIS pin is asserted, the watchdog timer is disabled, the timer is reset to its starting value and no faults are generated. When the watchdog timer is disabled, WD_2_RESET_FLAG bit is set to '0'. -40°C ≤ Tj ≤ 175°C; 3 V ≤ VCC ≤ 5.5 V, unless otherwise specified. Table 54. WD2 characteristics Symbol Parameter Test condition Min Typ Max Unit FWDvalid WD2 Frequency valid range ADV_CONFIG[14,13] = '00' 91 - 750 Hz ADV_CONFIG[14,13] = '01' - 1500 ADV_CONFIG[14,13] = '10' 46 - 750 ADV_CONFIG[14,13] = '11' - 1500 Toff WD2 timeout reset time ADV_CONFIG[14] = '0' 11 - 16.5 ms ADV_CONFIG[14] = '1' 22 - 33 TRH RESET re-engagement time between two consecutive assertion events 200 - - ms TWAIT WD2 quiescent time at power-up 200 - - ms RESET Note: In case that PRN frequency is higher than 1 kHz WDT counter is not cleared. PRN RESET RESET tOFF Toff TRL Toff Toff Pulse Width Counter WDT Counter 1ms (=1kHz) GADG2501171008PS |
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