www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP

(3.4)

NOTE 8

(5)

NOTE 8

(1.35) TYP

(0.65)

(1.3) TYP

(

0.2) TYP

VIA

(2.46)

(3.55)

PowerPAD TSSOP - 1.2 mm max height

PWP0016J

SMALL OUTLINE PACKAGE

4223595/A 03/2017

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

8. Size of metal pad may vary due to creepage requirement.

9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

TM

SEE DETAILS

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

SYMM

1

8

9

16

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

15.000

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

SOLDER MASK

OPENING

EXPOSED METAL

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED