DS5053 Rev 15

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L4995

Application information

36

Note:

The curve which describes the minimum ESR is derived from characterization data on the

regulator with connected ceramic capacitors which feature low ESR values (at 100 kHz).

Any capacitor with further lower ESR than the given plot value must be evaluated in each

and every case.

3.1

Voltage regulator

Voltage regulator uses a p-channel transistor as a regulating element. With this structure,

very low dropout voltage at current up to 500mA is obtained. The output voltage is regulated

up to transient input supply voltage of 40V. No functional interruption due to over-voltage

pulses is generated. A short circuit protection to GND is provided.

The voltage regulator is active when En is high.

Figure 28. Behavior of output current versus regulated voltage Vo

3.2

Reset

The reset circuit supervises the output voltage Vo. The Vo_th reset threshold is defined with

the in-ternal reference voltage and a resistor output divider. If the output voltage becomes

lower than Vo_th then Res goes low with a reaction time trr. The reset low signal is

guaranteed for an output voltage Vo greater than 1V.

When the output voltage becomes higher than Vo_th then Res goes high with a delay trd.

This delay is obtained by an internal oscillator.

The oscillator period is given by:

Equation 1

Tosc = [(VRhth-VRlth) x Ctr] / Icr + [(VRhth-VRlth) x Ctr] / Idr

Vo

Vo_ref

Iout

Ishort Ilim