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Figure 4. Timing of the ISO-interface

Figure 5. Timing of the drivers for the external MOS regarding the inputs DIR and PWM

t

TX

V

0.3

 V VCC

0.7

 V VCC

0.3

 V VCC

t

V

K

t

t KL

t KH

t Kr

t Kf

I K > I KSC

80 %

20%

0.55

 V VS

0.45

 V VS

VRX

t RXL

t RXH

0.3

 VVC C

0.7

 VVC C

ON

OFF

op en d r ain

tr ans is tor at

K- pin

t SH

50%

t

t

t

80%

20%

t

GHXLH

t

GHXr

t

GHXf

t

GHXHL

PWM

or

DIR

GHX

GLX

t

GLXHL

t

GLXf

t

GLXLH

t

GLXr

80%

20%