L9959 datasheet(32/49 Pages) STMICROELECTRONICS

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SPI functional description

L9959

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DocID027540 Rev 3

SPI functional description

5.1

General description

The SPI communication is based on a Serial Peripheral Interface structure using SS (SPI

Select), SI (Serial Data In), SO (Serial Data Out) and SCK (Serial Clock) signal lines. The

first data at pin SI is latched into the device with the first falling edge of the clock SCK after

the clock has changed from low to high, which is the second edge after SPI-Select has been

pulled to low.

5.1.1

SPI select (SS)

The SS input pin is used to select the serial interface of this device. When SS is high, the

output pin (SO) is in high impedance state. A low signal starts the serial communication. A

communication frame is the time between the falling edge of SS and its rising edge.

5.1.2

Serial data In (SI)

The SI input pin is used to transfer data serially into the device. The data applied to the SI is

sampled at the falling edge of the SCK signal.

5.1.3

Serial clock (SCK)

The Data Input (SI) is latched at the falling edge of Serial Clock SCK. Data on Serial Data

Out (SO) is shifted out at the rising edge of the serial clock (SCK). The serial clock SCK

must be active only during a frame (SS low).

5.1.4

Serial out (SO)

The content of the selected status or control register is transferred out of the device using

the SO pin on the rising edge of SCK. Each subsequent rising edge of the SCK will shift the

next bit out.

5.1.5

SPI communication flow

The SPI communication is started by sending an SPI instruction to the device beginning with

the MSB. The first two bits of this instruction are used as a device identifier (see Table 24:

SPI instruction byte). Whether the transfer is a read or a write access is determined by the

SPI command (see Table 26: Command overview). The SPI data is transmitted from the

device at the same time as the data is received, although on different SCK edges. While the

8-bit instruction is sent, the device responds with the check byte. Since the first two bits of

the instruction are used as a device identifier, the first two bits of the check byte are tristate.

This avoids bus conflicts on the SO line. During a write access, the 8-bit data byte is

received after the instruction byte. The device responds with 00H. In a read cycle the device

sends the 8-bit data, while the receive data bits are ignored (see Figure 19: Write access

and Figure 20: Read access). If an invalid instruction is detected, the register of the device

are not modified and the data byte FFH is transmitted instead of the data or 00H respectively.

The bit TRANS_F in the check byte is set in case of an invalid instruction and transmitted

during the next SPI-access. An instruction is invalid, if an unused instruction code is

detected, the previous transmission has not been completed or the number of clocks is not

equal to 16.

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