6.6.3 - AC Timings Requirements

Symbol

Parameter

Min.

Typ. Max.

Unit

Data Clock Period

50

-

-

ns

Duration of clock (CLK) pulse at high level

15

-

-

ns

Duration of clock (CLK) pulse at low level

15

-

-

ns

Set-up Time of data input before clock (low to high) transition

0

-

-

ns

Hold Time of data input after clock (low to high) transition

15

-

-

ns

Minimum Delay to latch (STB) after clock (low to high) transition

20

-

-

ns

Latch (STB) Low Level Pulse Duration

10

-

-

ns

Blanking (BLK) Pulse Duration

100

-

-

ns

Polarity (POL) Pulse Duration

100

-

-

ns

High Impedance (HIZ) Pulse Duration

100

-

-

ns

Set-up Time of Forward/Reverse Signal before Clock (low to high) transition

100

-

-

ns

6.6.4 - AC Timings Characteristics

Symbol

Parameter

Min.

Typ. Max.

Unit

Data Clock Period

50

-

-

ns

Logical Data Output Rise Time

-

TBD

30

ns

Logical Data Output Fall Time

-

TBD

30

ns

Delay of logic data output (high to low transition) after clock (CLK) transition

Delay of logic data output (low to high transition) after clock (CLK) transition

-

-

40

40

TBD

TBD

ns

ns

Delay of power output change (high to low transition) after clock (CLK) transition

Delay of power output change (low to high transition) after clock (CLK) transition

-

-

TBD

TBD

120

120

ns

ns

Delay of power output change (high to low transition) after Latch (STB) transition

Delay of power output change (low to high transition) after Latch (STB) transition

-

-

TBD

TBD

110

110

ns

ns

Delay of power output change (high to low transition) to Blank (BLK) or Polarity

(POL) transition

Delay of power output change (low to high transition) to Blank (BLK) or Polarity

(POL) transition

-

-

TBD

TBD

100

100

ns

ns

Delay of power output change (high to Hi-Z transition) after high impedance (HIZ) (5)

Delay of power output change (low to Hi-Z transition) after high impedance (HIZ) (5)

-

-

TBD

TBD

100

100

ns

ns

Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (5)

Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (5)

-

-

TBD

TBD

100

100

ns

ns

Power Output Rise Time (6)

-

-

150

ns

Power Output Fall Time (6)

-

-

150

ns

Notes : 5. See test diagram.

6 - STV7699 SPECIFICATIONS (continued)

CM17699

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