VNF1248F datasheet(22/79 Pages) STMICROELECTRONICS

22 / 79 page

Once the self-test is started, an internal current generator provides a current sink able to produce an additional

voltage offset of 100 mV on VDS monitor circuit inputs, to distinguish self-test execution from normal operation. In

order to ensure proper data conversions, special care must be taken to avoid VDS ADC saturation by keeping the

overall VDS sensed by the monitor circuit below the maximum scale range (VDS_ADC_CONV).

VDS detection self-test result is the difference between the converted value obtained during self-test execution

and the value already stored in SR#4 (VDS field), corresponding to the normal measurement performed during

operation; such delta measure result is stored in SR#5 (S_T_VDS field) together with the self-test status.

During self-test execution it is also possible to emulate the external FET VDS fault condition by playing with

programmable thresholds available through register CR#2 (VDS_THRS field) ; fault emulation result is stored in

SR#5 (S_T_VDS_MAX1 bit field).

To be noted that diagnostic fault for normal operation (VDS_MAX, SR#1) is inhibited during execution, while all

the others are kept enabled.

The transition from self-test state to unlocked state is automatically ensured after the test is completed (around 10

μs) or if the test is stopped through S_T_STOP = 1 (self-test aborted).

The transition from the self-test state to the locked state can occur in case of watchdog timeout or HWLO = 1

(self-test aborted).

When the self test is in execution if bypass and ext_fet are ON, this state is kept.

VNF1248F

Self-test

DS14109 - Rev 7

page 22/79

VNF1248F 数据表(PDF) 22 Page - STMicroelectronics