DP83867CSRGZ datasheet(22/129 Pages) TI2

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Figure 7-2. IEEE 1588 Message Timestamp Point

The SFD pulse output can be configured using the GPIO Mux Control registers, GPIO_MUX_CTRL1 (register

address 0x0171) and GPIO_MUX_CTRL2 (register address 0x0172). The ENHANCED_MAC_SUPPORT bit in

RXCFG (register address 0x0134) must also be set to allow output of the SFD.

For more information about configuring the DP83867's SFD feature, see the How to Configure DP83867 Start of

Frame application report (SNLA242).

7.3.2.1 SFD Latency Variation and Determinism

Time stamping packet transmission and reception using the RX_CTRL and TX_CTRL signals of RGMII is not

accurate enough for latency sensitive protocols. SFD pulses offers system designers a method to improve the

accuracy of packet time stamping. The SFD pulse, while varying less than RGMII signals inherently, still exhibits

latency variation due to the defined architecture of 1000BASE-T. This section provides a method to determine

when an SFD latency variation has occurred and how to compensate for the variation in system software to

improve timestamp accuracy.

In the following section the terms baseline latency and SFD variation are used. Baseline latency is the time

measured between the TX_SFD pulse to the RX_SFD pulse of a connected link partner, assuming an Ethernet

cable with all 4 pairs is matched in propagation time. In the scenario where all 4 pairs being are matched, a

1000BASE-T PHY won't have to align the 4 received symbols on the wire and won't introduce extra latency due

to alignment.

TX SFD

RX SFD

Baseline Latency

SFD Variation

Figure 7-3. Baseline Latency and SFD Variation in Latency Measurement

SFD variation is additional time added to the baseline latency before the RX_SFD pulse when the PHY must

introduce latency to align the 4 symbols from the Ethernet cable. Variation can occur when a new link is

established either by cable connection, auto-negotiation restart, PHY reset, or other external system effects.

During a single, uninterrupted link, the SFD variation remains constant.

The DP83867 can limit and report the variation applied to the SFD pulse while in the 1000Mb operating mode.

Before a link is established in 1000Mb mode, the Sync FIFO Control Register (register address 0x00E9) must be

set to value 0xDF22. The below SFD variation compensation method can only be applied after the Sync FIFO

Control Register has been initialized and a new link has been established. An acceptable methodology is to set

the Sync FIFO Control register value and then perform a software restart by setting the SW_RESTART bit[14] in

the Control Register (register address 0x001F) if a link is already present.

DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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