DP83867CSRGZR.B datasheet(21/129 Pages) TI2

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DEST * 16

DEST (6 bytes)

SRC (6 bytes)

MISC (X bytes, X >= 0)

))« )) (6 bytes)

MISC (Y bytes, Y >= 0)

CRC (4 bytes)

MAGIC pattern

SecureOn Password (6 bytes)

Only if Secure-On is enabled

Figure 7-1. Magic Packet Structure

7.3.1.2 Magic Packet Example

The following is an example Magic Packet for a Destination Address of 11h 22h 33h 44h 55h 66h and a

SecureOn Password 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh with the MAC ADDRESS = 00:28:29:74:E2:F8

DESTINATION SOURCE MISC 00 28 29 74 E2 F8 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11

22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44

55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11

22 33 44 55 66 11 22 33 44 55 66 2A 2B 2C 2D 2E 2F MISC CRC

7.3.1.3 Wake-on-LAN Configuration and Status

Magic Packet Detection Registers

DP83867 Address

Receive Configuration Register

Reg 0x134

Receive Status Register

Reg 0x135

MAC Destination Address Registers

Reg 0x136-0x138

Receive Secure-ON Password Registers

Reg 0x139 - 0x13B

Byte Mask

Reg 0x15C - 0x15F

DP83867's Magic Packet functionality is only applicable for Unicast packets only.

7.3.2 Start of Frame Detect for IEEE 1588 Time Stamp

The DP83867 supports an IEEE 1588 indication pulse at the SFD (start frame delimiter) for the receive and

transmit paths. The pulse can be delivered to various pins. The pulse indicates the actual time the symbol is

presented on the lines (for transmit), or the first symbol received (for receive). We are adjusting baseline latency

to help with SFD variation. The baseline latency can be adjusted through register. Each increment of phase

value is an 8ns step.

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DP83867CS, DP83867IS, DP83867E

SNLS504F – OCTOBER 2015 – REVISED JANUARY 2025

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