STPM11ATR datasheet(30/46 Pages) STMICROELECTRONICS

30 / 46 page

Theory of operation

STPM11, STPM12, STPM13, STPM14

30/46

Doc ID 13167 Rev 8

7.16

Mode signals

The STPM1x includes four mode signals. These signals change some of the operation of

the STPM1x. The mode signals are not retained when the STPM1x supply is not available

and then they are cleared when a POR occurs.

The mode signals bit can be written using the normal writing procedure of the CFGI

interface (see CFGI par. 7.17)

– RD mode signal has been already described in par. 7.15 (configuring the STPM1x),

but there is another implied function of the signal RD. When it is set, each sense

amplifier is disconnected from corresponding antifuse element and this way, its 3 V

NMOS gate is protected from the high voltage of VOTP during permanent write

operation. This means that as long as the VOTP voltage reads more than 3 V, the

signal RD should be set.

– PUMP. When set, the PUMP mode signal transforms the MOP and MON pins to act

as driving signals to implement a charge-pump DC-DC converter (see Figure 23).

This feature is useful in order to boost the VCC supply voltage of the STPM1x to

generate the VOTP voltage (14 V to 20 V) needed to program the OTP anti-fuse

elements.

– WE (write Enable): This mode signal is used to permanently write to the OTP anti-

fuse element. When this bit is not set, any writing to the configuration bit is recorded

in the shadow latches. When this bit is set, the writing is recorded both in the shadow

latch and in the OTP anti-fuse element.

7.17

CFGI: configuration interface

The CFGI interface supports a simple serial protocol, which is implemented in order to

enable the configuration of STPM1x which allows writing the mode bits and the

configuration bits (temporarily or permanently);

Four pins of the device are dedicated to this purpose: SCS, SYN-NP, SCLNCN, SDATD.

SCS, SYN-NP, SCL-NLC and SDATD are all input pins. A high level signal for these pins

means a voltage level higher than 0.75 x VCC, while a low level signal means a voltage value

lower than 0.25 x VCC.

Table 16.

Mode signals description

Signal

Name

Bit

Value

Status

Binary

Command

Hex

Command

PUMP

MOP and MON operate normally

0111001x

72 or 73

MOP and MON provide the driving signals to implement a

charge-pump DC-DC converter

1111001x

F2 or F3

The 56 Configuration bits originated by OTP anti-fuses

0111101x

7A or 7B

The 56 Configuration bits originated by shadow latches

1111101x

FA or FB

Any writing in the configuration bits is recorded in the shadow

latches

0111110x

7C or 7D

Any writing in the configuration bits is recorded both in the

shadow latches and in the OTP anti-fuse elements

1111110x

FC or FD

Obsolete

Product(s)

- Obsolete

Product(s)

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