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M41TC8025 数据表(PDF) 13 Page - STMicroelectronics |
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M41TC8025 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 41 page  DocID022873 Rev 4 13/41 M41TC8025 Operation Figure 9. WRITE mode sequence 2.2.8 I2C timeout function The M41TC8025 device incorporates a timeout function for the I2C bus. When communicating with the M41TC8025 device, the series of operations from transmitting the START condition to transmitting the STOP condition should be kept within 0.95 seconds. If the series of operations require more than 0.95 seconds, the I2C bus interface will be automatically reset to standby mode by this timeout function. If timeout happens during a data byte transfer, the data byte being transferred (read or write) will not complete successfully. Data written into the device will not be acknowledged and the address pointer remains unchanged. If a read is in progress, the data bits after timeout will be read as 1 and the address pointer will remain unchanged. 2.3 Register description The register map within the M41TC8025 and the default values after initial power-up are given in Table 4 on page 14. Register 00h to 06h are used for the clock and calendar. Refer to Section 2.4: Clock and calendar on page 15 for the detailed function and setting of the registers. Register 07h is a RAM byte for the user. Register 08h to 0Ah are alarm registers for the alarm interrupt. Refer to Section 2.8: Alarm interrupt function on page 25 for the detailed function and setting of the registers. Register 0Bh to 0Ch are timer registers for the fixed-cycle interrupt timer target value setting. Refer to Section 2.6: Fixed-cycle timer interrupt on page 18 for the detailed function and setting of the registers. Register 0Dh to 0Fh are status and control registers. The detailed function of each bit is described in each of the function sections. Obsolete Product(s) - Obsolete Product(s) |
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