Operation

M41TC8025

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DocID022873 Rev 4

Figure 17. Alarm interrupt timing sequence

1. The alarm condition of alarm hours, minutes, date or day is set in advance along with the WADA bit. The alarm event only

happens when the current clock and calendar counts to match the alarm condition. Even if the current date/time is set as

the alarm condition, the alarm will not occur until the counter counts up to the current date/time (i.e., an alarm will occur the

next time, not immediately).

2. When an alarm event occurs, the AF bit is set to 1.

3. When the AF=1, it remains until it is reset to 0 by the user.

4. If AIE=1 when an alarm event occurs, the IRQ pin output is driven low and the status is then held until it is released to Hi-Z

by the AF bit reset to 0 or the AIE bit set to 0.

5. If the AIE is set to 0 while the IRQ pin is low, the IRQ pin is released to Hi-Z immediately.

6. If the AF bit is reset to 0 while the IRQ pin is low, the IRQ pin is released to Hi-Z immediately.

7. If AIE=0 when an alarm event occurs, the IRQ pin status remains Hi-Z.

2.9

Relationship between the three interrupts

The IRQ pin is a shared output pin for the above three types of interrupts. It outputs the logic

OR'ed result of these interrupts.

When an interrupt has occurred and the IRQ pin is pulled low, the status of the UF, TF and

AF flags will indicate which interrupt(s) has(have) occurred.

If the user sets RESET to 1 when IRQ is low, the IRQ pin releases to Hi-Z immediately.

2.10

Low-voltage detection

The M41TC8025 has two register bits in 0Eh to indicate the voltage low levels as highlighted

in Table 22.

Table 22. Battery voltage low related register bits

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OEh

Flag register

0

0

UF

TF

AF

0

VLF

VDET

Obsolete

Product(s)

- Obsolete

Product(s)