M41T93RMY6F datasheet(13/56 Pages) STMICROELECTRONICS

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M41T93

Operation

By definition a device that gives out a message is called “transmitter,” the receiving device

that gets the message is called “receiver.” The device that controls the message is called

“master.” The devices that are controlled by the master are called “slaves.”

The E input is used to initiate and terminate a data transfer. The SCL input is used to

synchronize data transfer between the master (micro) and the slave (M41T93) device.

The SCL input, which is generated by the microcontroller, is active only during address and

data transfer to any device on the SPI bus (see Figure 5 on page 10).

The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode

0: (CPOL, CPHA) = (0,0).

For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and

output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2 and

Figure 6 on page 10).

There is one clock for each bit transferred. Address and data bits are transferred in groups

of eight bits. Since only 32 addresses are required, address bit 6 is a “don’t care”.

2.2

READ and WRITE cycles

Address and data are shifted MSB first into the serial data input (SDI) and out of the serial

data output (SDO). Any data transfer considers the first bit to define whether a READ or

WRITE will occur. This is followed by seven bits defining the address to be read or written.

Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE

operation. The address is always the second through the eighth bit written after the enable

(E) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is

a '0,' one or more READ cycles will occur (see Figure 7 and Figure 8 on page 14).

Data transfers can occur one byte at a time or in multiple byte burst mode, during which the

address pointer will be automatically incremented. For a single byte transfer, one byte is

read or written and then E is driven high. For a multiple byte transfer all that is required is

that E continue to remain low. Under this condition, the address pointer will continue to

increment as stated previously. Incrementing will continue until the device is deselected by

taking E high. The address will wrap to 00h after incrementing to 3Fh.

Reads and writes of the internal counters are performed through a set of buffer/transfer

registers as shown in Figure 9 on page 17. At the start of any read or write cycle, the

counters are copied to the buffer/transfer registers. Thus, the time/date is effectively frozen

for the user until the access is completed, although the counters are still running and

maintaining the correct time.

Note:

This is true both in READ and WRITE mode.

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