S24CS02A datasheet(16/47 Pages) SII

16 / 47 page

2-WIRE CMOS SERIAL E2PROM

S-24CS01A/02A/04A/08A

Rev.4.4_00

Seiko Instruments Inc.

7. Read

7. 1 Current Address Read

Either in writing or in reading the E

2PROM holds the last accessed memory address, internally

incremented by one. The memory address is maintained as long as the power voltage is higher than the

current address hold voltage VAH.

The master device can read the data at the memory address of the current address pointer without

assigning the word address as a result, when it recognizes the position of the address pointer in the

2PROM. This is called "Current Address Read".

In the following the address counter in the E

2PROM is assumed to be “n”.

When the E

2PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1”

following a start condition, it responds with an acknowledge. However, the page address (P0) in S-

24CS04A and the page address (P1 and P0) in S-24CS08A become invalid and the memory address of

the current address pointer becomes valid.

Next an 8-bit data at the address "n" is sent from the E

2PROM synchronous to the SCL clock. The

address counter is incremented at the falling edge of the SCL clock for the 8th bit data, and the content of

the address counter becomes n

+1.

The master device outputs stop condition not an acknowledge ,the reading of E

2PROM is ended.

1 0 1 0

DEVICE

ADDRESS

SDA LINE

A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

ADR INC

DATA

NO ACK from

Master Device

Remark1. A1 is P1 in S-24CS08A.

2. A0 is P0 in S-24CS04A/08A.

Figure 16 Current Address Read

Attention should be paid to the following point on the recognition of the address pointer in the E

2PROM.

In the read operation the memory address counter in the E

2PROM is automatically incremented at every

falling edge of the SCL clock for the 8th bit of the output data. In the write operation, on the other hand,

the upper bits of the memory address (the upper bits of the word address and page address)

*1 are left

unchanged and are not incremented at the falling edge of the SCL clock for the 8th bit of the received

data.

*1.

S-24CS01A/02A is the upper 5 bits of the word address.

S-24CS04A is the upper 4 bits of the word address and the page address P0.

S-24CS08A is the upper 4 bits of the word address and the page address P1 and P0.

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