IS25LE512M-RGLA3:P-TY datasheet(91/189 Pages) ISSI

91 / 189 page

IS25LE512M

IS25WE512M

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A6

06/16/2025

8.14 BLOCK ERASE OPERATION (BER32K:52h or 4BER32K:5Ch, BER64K/256K:D8h or

4BER64K/256K:DCh)

A Block Erase (BER) instruction erases a 32/64 or 32/256 Kbyte block. Before the execution of a BER instruction,

the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically

after the completion of a block erase operation.

• 52h/D8h (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• 52h/D8h (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• 5Ch/DCh is followed by a 4-byte address (A31-A0)

The BER instruction code and three or four address bytes as above are input via SI. Erase operation will start

immediately after the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control

logic automatically handles the erase voltage and timing.

Figure 8.31 Block Erase (64K/256K) Sequence In SPI Mode (D8h [EXTADD=0], 3-byte address)

Instruction = D8h

CE #

SCK

3-byte Address

High Impedance

...

Mode 3

Mode 0

Figure 8.32 Block Erase (64K/256K) Sequence In SPI Mode (D8h [EXTADD=1] or DCh, 4-byte address)

4-byte Address

Instruction = D8h/DCh

CE #

SCK

High Impedance

...

Mode 3

Mode 0

IS25LE512M-RGLA3:P-TY 数据表(PDF) 91 Page - Integrated Silicon Solution, Inc