IS25LP256D-RJLA3-TY datasheet(56/179 Pages) ISSI

56 / 179 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A15

08/05/2024

8.4 FAST READ OPERATION (FRD, 0Bh or 4FRD, 0Ch)

The FRQO/4FRQO instruction is used to read memory data on four output pins. A Quad Enable (QE) bit of

status Register must be set to “1” before sending FRQO/4FRQO instruction.

• 0Bh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

• 0Bh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

• 0Ch is followed by a 4-byte address (A31-A0)

The Fast Read instruction code is followed by three or four address bytes as above and dummy cycles

(configurable, default is 8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK.

Then the first data byte from the address is shifted out on the SO line, with each bit shifted out at a maximum

frequency fCT, during the falling edge of SCK.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single Fast Read instruction. The Fast Read

instruction is terminated by driving CE# high (VIH).

If the Fast Read instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction

is ignored without affecting the current cycle.

IS25LP256D-RJLA3-TY 数据表(PDF) 56 Page - Integrated Silicon Solution, Inc