LP8733 datasheet(26/86 Pages) TI2

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Time

Voltage

Ramp for Buck

BUCKx_CTRL2(SLEW_RATEx[2:0])

BUCKx_VSET /

LDOx_VSET

INT_BUCK(BUCKx_PG_INT) /

INT_LDO(LDOx_PG_INT)

nINT

Host clears

interrupt

Powergood

interrupt

Powergood

BUCK_STAT(BUCKx_STAT) /

LDO_STAT(LDOx_STAT)

Powergood

BUCK_STAT(BUCKx_PG_STAT) /

LDO_STAT(LDOx_PG_STAT)

Host clears

interrupt

Powergood

interrupt

BUCK_MASK(BUCKx_PGF_MASK)=0

BUCK_MASK(BUCKx_PGR_MASK)=0

LDO_MASK(LDOx_PGF_MASK)=0

LDO_MASK(LDOx_PGR_MASK)=0

Figure 7-8. Regulator Output Voltage Change

During an LDO voltage change, the internal reference for the Power-Good detection is also changed. For this

reason when the output voltage is changing, toggling of the Power-Good signal may still indicate a valid output.

This period takes less than 100 µs and after that time the Power-Good gives correct value.

7.3.6 Enable and Disable Sequences

The LP8733xx-Q1 device supports start-up and shutdown sequencing with programmable delays for different

regulator outputs using a single EN control signal. The Buck regulator is selected for delayed control with:

• The BUCKx_EN = 1 in the BUCKx_CTRL_1 register

• The BUCKx_EN_PIN_CTRL = 1 in the BUCKx_CTRL_1 register

• The BUCKx_VSET[7:0] bits in the BUCKx_VOUT register defines the voltage when the EN pin is high

• The delay from the rising edge of the EN pin to the regulator enable is set by the

BUCKx_STARTUP_DELAY[3:0] bits in the BUCKx_DELAY register.

• The delay from the falling edge of the EN pin to the regulator disable is set by the

BUCKx_SHUTDOWN_DELAY[3:0] bits in the BUCKx_DELAY register.

LP8733-Q1

SNVSB64A – JUNE 2019 – REVISED JUNE 2021

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