Reset

Reset Removal

1024 System Clocks

VCC

3.7 V (Max)

3.0 V (Typ)

2.2 V (Min)

Internal Reset

System Clock

Don’t Care

t(SCKH)

t(SCY)

System Clock (SCK)

t(SCKL)

2.0 V

0.8 V

H

L

13

PCM1753, PCM1754, PCM1755

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SLES092E – APRIL 2003 – REVISED JULY 2019

Product Folder Links: PCM1753 PCM1754 PCM1755

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Copyright © 2003–2019, Texas Instruments Incorporated

Feature Description (continued)

(1)

This system clock rate is not supported for the given sampling frequency.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING

FREQUENCY

SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

1152 fS

8 kHz

1.024

1.536

2.048

3.072

4.096

6.144

9.216

16 kHz

2.048

3.072

4.096

6.144

8.192

12.288

18.432

32 kHz

4.096

6.144

8.192

12.288

16.384

24.576

36.864

44.1 kHz

5.6448

8.4672

11.2896

16.9344

22.5792

33.8688

(1)

48 kHz

6.144

9.216

12.288

18.432

24.576

36.864

(1)

88.2 kHz

11.2896

16.9344

22.5792

33.8688

45.1584

(1)

(1)

96 kHz

12.288

18.432

24.576

36.864

49.152

(1)

(1)

192 kHz

24.576

36.864

(1)

(1)

(1)

(1)

(1)

Figure 20. System Clock Input Timing

8.3.1.2 Power-On Reset Functions

The PCM175x devices include a power-on reset function. Figure 21 shows the operation of this function. With the

system clock active and VCC > 3 V (typical, 2.2 V to 3.7 V), the power-on reset function is enabled. The

initialization sequence requires 1024 system clocks from the time VCC > 3 V (typical, 2.2 V to 3.7 V).

During the reset period (1024 system clocks), the analog output is forced to the bipolar zero level, or VCC/2. After

the reset period, an internal register is initialized in the next 1/fS period and if SCK, BCK, and LRCK are provided

continuously, the PCM175x devices provide proper analog output with unit group delay against the input data.

Figure 21. Power-On Reset Timing