PIN DESCRIPTION

Name

Pi n

Type (*)

N

Description

VPO

+

O

1

The Non-inverting Output of the Receive Power Amplifier

GNDA

GND

2

Analog Ground. All signals are referenced to this pin.

VPO

-

O

3

The Inverting Output of the Receive Power Amplifier

VPI

I

4

Inverting Input to the Receive Power Amplifier. Also powers down both

O

5

Analog Output of the Receive Filter.

S

6

±5%

I

7

I

8

edge

I

9

vary from 64KHz to 2.048MHz.

Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz

for both transmit and receive directions (see table 1). This input has an

internal pull-up.

I

10

Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May

high, the device is powered down.

I

11

Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May

I

12

O

13

The TRI-STAT E

I

14

timing details.

O

15

Open drain output which pulses low during the encoder time slot. Must to

be grounded if not used.

ANLB

I

16

Analog Loopback Control Input. Must be set to logic ’0’ for normal

operation. When pulled to logic ’1’, the transmit filter input is disconnected

from the output of the transmit preamplifier and connected to the VPO

+

output of the receive power amplifier.

O

17

Analog output of the transmit input amplifier. Used to set gain externally.

-

I

18

Inverting input of the transmit input amplifier.

+

I

19

Non-inverting input of the transmit input amplifier.

S

20

±5%

(*) I: Input, O: Output, S: Power Supply.

TRI- STATE

® is a trademark of National Semiconductor Corp.

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

3/18