ETC5064FN datasheet(4/18 Pages) STMICROELECTRONICS

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FUNCTIONAL DESCRIPTION

POWER-UP

When power is first applied, power-on reset circuitry

initializes the device and places it into the power-

down mode. All non-essential circuits are deacti-

vated and the DX and VFRO outputs are put in high

impedancestates. To power-up the device, a logical

low level or clock must be applied to the

MCLKR/PDN pin and FSX and/or FSR pulses must

be present. Thus 2 power-down control modes are

available. The first is to pull the MCLKR/PDN pin

high; the alternative is to hold both FSX and FSR in-

puts continuously low. The device will power-down

approximately 2 ms after the last FSX pulse. The

TRI-STATE PCM data output, DX, will remain in the

high impedance state until the second FSX pulse.

SYNCHRONOUS OPERATION

For synchronous operation, the same master clock

and bit clock should be used for both the transmit

and receive directions. In this mode, a clock must be

applied to MCLKX and the MCLKR/PDN pin can be

used as a power-down control. A low level on

MCLKR/PDN powers up the device and a high level

powers down the device. In either case, MCLKX will

be selected as the master clock for both the transmit

and receive circuits. A bit clock must also be applied

to BCLKX and the BCLR/CLKSEL can be used to se-

lect the proper internal divider for a master clock of

1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544

MHz operation, the device automatically compen-

sates for the 193 rd clock pulse each frame.

With a fixed level on the BCLKR/CKSEL pin, BCLKX

will be selected as the bit clock for both the transmit

and receive directions. Table 1 indicates the fre-

quencies of operation which can be selected, de-

pending on the state of BCLKR/CLKSEL. In this syn-

chronous mode, the bit clock, BCLKX, may be from

64 kHz to 2.048 MHz, but must be synchronouswith

MCLKX.

Each FSX pulse begins the encoding cycle and the

PCM data from the previous encode cycle is shift out

of the enabled DX output on the positive edge of

BCLKX. After 8 bit clock periods, the TRISTATE DX

output is returned to a high impedance state. With an

FSR pulse, PCM data is latched via the DR input on

the negativeedge of BCLKX (or on BCKLR if running).

FSX and FSR must be synchronous with MCLKX/R.

ASYNCHRONOUS OPERATION

For asynchronous operation, separate transmit and

receive clocks may be applied. MCLKX and MCLKR

must be 2.048 MHz for the ETC5067 or 1.536 MHz,

1.544 MHz for the ETC5064, and need not be syn-

chronous. For best transmission performance, how-

ever, MCLKR should be synchronouswith MCLKX,

which is easily achieved by applyingonly static logic

levels to the MCLKR/PDN pin. This will automatically

connectMCLKX toall internal MCLKR functions(see

pin description). For 1.544 MHz operation, the de-

vice automatically compensates for the 193rd clock

pulse each frame. FSX starts each encoding cycle

and must be synchronous with MCLKX and BCLKX.

FSR starts each decoding cycle and must be syn-

chronous with BCLKR.BCLKR must be a clock, the

logic levels shown in Table 1 are not valid in asyn-

chronous mode. BCLKX and BCLKR may operate

from 64kHz to 2.048 MHz.

SHORT FRAME SYNC OPERATION

The device can utilize either a short frame sync

pulse or a long frame sync pulse.Upon power initiali-

zation, the device assumes a short frame mode. In

this mode, both frame sync pulses. FSX and FSR,

must be one bit clock period long, with timing rela-

tionships specified in figure 2. With FSX high during

a falling edge of BCLKR, the next rising edge of

BCLKX enables the DX TRI-STATE output buffer,

which will output the sign bit. The following seven ris-

ing edges clock out the remaining seven bits, and

the next falling edge disables the DX output. With

FSR high during a falling edge of BCLKR (BCLKX in

synchronous mode), the next falling edge of BCLKR

latches in the sign bit. The following seven falling

edges latch in the seven remaining bits. Both de-

vices may utilize the short frame sync pulse in syn-

chronous or asynchronous operating mode.

LONG FRAME SYNC OPERATION

To use the long frame mode, both the frame sync

pulses, FSX and FSR, must be three or more bit clock

periods long, with timing relationships specified in

figure 3. Based on the transmit frame sync FSX,the

device will sense whether short or long frame sync

Table 1: Selection of Master Clock Frequencies.

BCLKR/CLKSEL

Master Clock

Frequency Selected

ETC5067

ETC5067-X

ETC5064

ETC5064-X

Clocked

2.048MHz

1.536MHz or

1.544MHz

1.536MHz or

1.544MHz

2.048MHz

1 (or open circuit)

2.048MHz

1.536MHz or

1.544MHz

ETC5064 - ETC5064-X - ETC5067 - ETC5067-X

4/18

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