AD3530 datasheet(29/49 Pages) AD

29 / 49 page

Data Sheet

AD3530/AD3530R

APPLICATIONS INFORMATION

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Rev. A | 29 of 49

Figure 74. DAC Update Flowchart

Option 1 (Immediate Update, Unique Data, No

LDAC, and Single and Multiple Channels)

Option 1 allows the immediate update of the DAC_CHn registers

after writing the whole 16-bit data. An LDAC is not required.

Option 1 is applicable to both single channel and multiple channel

updates in single instruction or stream modes.

Figure 75. Option 1 Example: Write to DAC_CH0 Register; Single Instruction

Mode and Address Descending

A single instruction is sent with the descending mode selected. The

higher address of the multibyte register is called on the instruction

phase (0xD4, DAC_CH0 register, followed by two 8-bit data) that

updates the output immediately after the last SCLK.

Option 2 (Controlled Update, Unique Data,

Hardware LDAC, and Single and Multiple

Channels

Option 2 allows controlled update timing of the DAC_CHn registers

from the INPUT_CHn registers through a hardware LDAC.

Applicable to both single channel and multiple channel updates in

single instruction or stream modes.

AD3530 数据表(PDF) 29 Page - Analog Devices