AD3530 datasheet(30/49 Pages) AD

30 / 49 page

Data Sheet

AD3530/AD3530R

APPLICATIONS INFORMATION

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Rev. A | 30 of 49

Figure 76. Option 2 Example: Write to Input_Ch7 to Input_Ch0 Registers;

Hardware LDAC Enabled; Stream Mode and Address Descending

A single instruction is sent to write to the HW_LDAC_EN_0 regis-

ter, enabling hardware LDAC for the selected channels. Then, a

stream mode is initiated, in default descending mode, writing to the

INPUT_CH7 first up to INPUT_CH0. The LDACB is asserted at the

end of the stream updating the DAC registers and the DAC output

(if the correct LDACB timing is observed).

Option 3 (Controlled Update, Unique Data,

Software LDAC, and Single and Multiple

Channels)

Option 3 allows controlled update timing of the DAC_CHn registers

from the INPUT_CHn registers through the software LDAC.

This option is applicable to both single channel and multiple chan-

nel updates in single instruction and stream modes.

Figure 77. Option 3 Example: Write to INPUT_CH7 and INPUT_CH6 Registers,

with a software LDAC, Stream Mode and Address Descending

Similar to Option 2, except, a software LDAC function is used

instead of a hardware LDAC. The SW_LDAC_EN_0 register deter-

mines which channel gets affected by a software LDAC command.

The DAC registers and DAC outputs are updated with the input

data written after the last SCLK of the SW LDAC command.

Option 4 (Immediate Update, Same Data, No

LDAC, and Multiple Channels)

Option 4 allows the immediate and simultaneous up-

date of multiple DAC_CHn registers identified by MUL-

TI_DAC_SEL_0(MD_SEL_CH_n) bitfields with the same data. Data

is contained in MULTI_DAC_CH register and update is initiated

after writing the whole 16-bit data. An LDAC is not required.

Option 4 is ideal for multiple channel updates in both single instruc-

tion and stream mode.

Figure 78. Option 4 Example: Write to MULTI_DAC_CHn Register, Stream

Mode (Loop) and Address Descending

A write instruction is sent to Multi_DAC_Sel_0 register, enabling

multi DAC function for the selected channels. With stream mode

descending enabled, the next commands are the data for the

adjacent multi-byte register 0xE3 (and 0xE2) MULTI_DAC_CH.

Assuming that STREAM_MODE(LOOP_COUNT) is set to 0x3, the

succeeding data stream loops back to the start address, 0xE4, and

repeats the process, until CSB is deasserted.

Option 5 (Controlled Update, Same Data,

Hardware LDAC, and Multiple Channels)

Option 5 allows controlled update timing of multiple DAC_CHn

registers identified by MULTI_INPUT_SEL_0(MI_SEL_CH_n) and

HW_LDAC_EN_0(HLD_EN_CH_n) bitfields with the same data.

Data is contained in MULTI_INPUT_CH register and update is

initiated by providing a valid LDACB pulse.

Option 5 is ideal for multiple channel updates in both single instruc-

tion and stream modes.

Figure 79. Option 5 Example: Write to MULTI_INPUT_CH Register with a

Hardware LDAC, Stream Mode (Loop) and Address Ascending

Option 5 is similar to Option 2 except this option makes use

of the MULTI_INPUT_SEL_0 and MULTI_INPUT_CH registers to

select and update the input registers of multiple DAC channels.

The LDACB is asserted after each loop ends, updating the DAC

registers and the DAC outputs (when correct LDAC is observed).

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