STPM32_V02 datasheet(53/89 Pages) STMICROELECTRONICS

53 / 89 page

Bit position

Description

Default value

Access mode

IRQ CR

mask for UART timeout error

mask for UART CRC error

•

SPI RX overrun: occurs when two consecutive write transactions are too fast and close to each other

•

SPI TX underrun: occurs when a read-back operation (= write then read the same register) or latch/read is

too fast

•

SPI CRC error: CRC error detected

•

UART/SPI write address error: write address out of range (not write address not writable)

•

UART/SPI read address error: read address out of range (not read address not readable)

•

SPI TX empty: transmission buffer empty (for SPI diagnostic, not recommended for normal IRQ operations)

•

SPI RX full: reception buffer full (for SPI diagnostic, not recommended for normal IRQ operations)

•

UART TX overrun: occurs when master and slave have different baud rates and master transmits before

reception has ended

•

UART RX overrun: active when received data have not been correctly processed

•

UART noise error: noisy bit detected

•

UART frame error: missing stop bit detected

•

UART timeout error: timeout counter expired

•

UART CRC error: CRC error detected

•

UART break: break frame (all zeros) received.

Read-write status bits are set by the occurrence of the related event and are not reset when the event ceases, on

contrary master can only reset them transmitting a write sequence addressed to memory location 0x28.

STPM32, STPM33, STPM34

Communication protocol

DS10272 - Rev 13

page 53/89

STPM32 数据表(PDF) 53 Page - STMicroelectronics

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