Refer to Figure 7-9 for IMON output versus load current plot. Figure 9-12 illustrates IMON performance.

IMON

VIN

VOUT

IIN

Figure 9-12. IMON Response During a Load Step

The IMON pin must not have a bypass capacitor to avoid delay in the current monitoring information.

9.3.7 FAULT Response (FLT)

The FLT open-drain output asserts (active low) under the faults events such as undervoltage, overvoltage,

overload, power limiting, ILIM pin short, and thermal shutdown conditions. The device is designed to eliminate

false reporting by using an internal de-glitch circuit for fault conditions without the need for an external circuitry.

FLT can be left open or connected to GND when not used.

9.3.8 Power Good Output (PGOOD)

The devices feature an open drain Power Good (PGOOD) indicator output. PGOOD can be used for enable-

disable control of the downstream loads like DC/DC converters. PGOOD goes high when the internal FET’s gate

is enhanced. PGOOD goes low when the internal FET turns OFF during a fault event or when SHDN is pulled

low. There is a deglitch of 11.5 msec (typical), tPGOODR, at the rising edge and 10 msec (typical), tPGOODF, on

falling edge. PGOOD is a rated for 60 V and can be pulled to IN or OUT through a resistor.

9.3.9 IN, P_IN, OUT and GND Pins

Connect a minimum of a 0.1-µF capacitor across IN and GND. Connect P_IN and IN together. Do not leave any

of the IN and OUT pins un-connected.

9.3.10 Thermal Shutdown

The device has a built-in overtemperature shutdown circuitry designed to protect the internal FET if the junction

temperature exceeds T(TSD), 165°C (typical). After the thermal shutdown event, depending upon the mode of

fault response configured as shown in Table 9-1, the device either latches off or commences an auto-retry cycle

of 648 msec (typical), t(TSD_retry) after TJ < ((TSD) – 11°C). During the thermal shutdown, the fault pin FLT pulls low

to indicate a fault condition.

9.3.11 Low Current Shutdown Control (SHDN)

The internal and the external FET and hence the load current can be switched off by pulling the SHDN pin below

0.8-V threshold with a micro-controller GPIO pin or can be controlled remotely with an opto-isolator device. The

device quiescent current reduces to 21 μA (typical) in shutdown state. To assert SHDN low, the pull down must

have sinking capability of at least 10 µA. To enable the device, SHDN must be pulled up to at least 2 V. Once

the device is enabled, the internal FET turns on with dVdT mode.Figure 9-13 and Figure 9-14 illustrate the

performance of SHDN control.

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TPS1663

SLVSET9F – SEPTEMBER 2018 – REVISED FEBRUARY 2023

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