7.5 Electrical Characteristics (continued)

–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 60 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN,

C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V(dVdTmax)

dVdT maximum capacitor voltage

3.8

4.17

4.75

V

R(dVdT)

dVdT discharging resistance

10

16.6

26.6

Ω

CURRENT MONITOR OUTPUT (IMON)

GAIN(IMON)

Gain factor I(IMON):I(OUT)

0.6 A ≤ I(OUT) < 2 A

25.66

27.9

30.14

µA/A

2 A ≤ I(OUT) ≤ 6 A

26.22

27.9

29.58

µA/A

LOW IQ SHUTDOWN ( SHDN) INPUT

V( SHDN)

Open circuit voltage

I( SHDN) = 0.1 µA

2.48

2.7

3.3

V

V(SHUTF)

SHDN threshold voltage for low IQ

shutdown, falling

0.8

V

V(SHUTR)

SHDN threshold rising

2

V

I( SHDN)

Leakage current

V( SHDN) = 0 V

–10

µA

FAULT FLAG ( FLT): ACTIVE LOW

R( FLT)

FLT Pull-down resistance

36

70

130

Ω

I( FLT)

FLT Input leakage current

0 V ≤ V( FLT) ≤ 60 V

–150

6

150

nA

POWER GOOD (PGOOD)

R(PGOOD)

PGOOD Pull-down resistance

36

70

130

Ω

I(PGOOD)

PGOOD Input leakage current

0 V ≤ V(PGOOD) ≤ 60 V

–150

6

150

nA

THERMAL PROTECTION

T(J_REG)

Thermal regulation set point

136

145

154

°C

T(TSD)

Thermal shutdown (TSD) threshold,

rising

165

°C

T(TSDhyst)

TSD hysteresis

11

°C

MODE

MODE_SEL

Mode selection

MODE = Open

Latch

MODE = Short to GND

Auto –

Retry

(1)

Parameter specified by design and characterization, not tested in production

7.6 Timing Requirements

–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 60 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN,

C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

UVLO INPUT (UVLO)

UVLO_ton(dly)

UVLO switch turnon delay

UVLO↑ (100 mV above V(UVLOR)) to

V(OUT) = 100 mV, C(dVdT) ≥ 10

nF, [C(dVdT) in nF]

742 +

49.5 x

C(dVdT)

µs

UVLO_toff(dly)

UVLO switch turnoff delay

UVLO↓(20 mV below V(UVLOF)) to FLT↓

9

11

16

µs

tUVLO_FLT(dly)

UVLO to Fault de-assertion delay

UVLO↑ to FLT ↑ delay

500

617

700

µs

OVER VOLTAGE PROTECTION INPUT (OVP)

OVP_toff(dly)

OVP switch turnOFF delay

OVP↑ (20 mV above V(OVPR)) to FLT↓

8.5

11

14

µs

OVP_ton(dly)

OVP switch disable delay

OVP↓ (100 mV below V(OVPF)) to FET

ON , C(dVdT) ≥ 10 nF, [C(dVdT) in nF]

150 +

49.5 x

C(dVdT)

µs

tOVC(dly)

Maximum duration in over voltage

clamp operation

TPS16632 only

162

ms

TPS1663

SLVSET9F – SEPTEMBER 2018 – REVISED FEBRUARY 2023

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