ADL5519ACPZ-R7 datasheet(19/40 Pages) AD

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ADL5519

Rev. 0 | Page 19 of 40

THEORY OF OPERATION

The ADL5519 is a dual-channel, six-stage demodulating loga-

rithmic amplifier that is specifically designed for use in RF

measurement and power control applications at frequencies

up to 10 GHz. The ADL5519 is a derivative of the AD8317

logarithmic detector/controller core. The ADL5519 maintains

tight intercept variability vs. temperature over a 50 dB range.

Each measurement channel offers performance equivalent to

that of the AD8317. The complete circuit block diagram is

shown in Figure 50.

INHA

INHB

INLB

COMR

PWDN

COMR

INLA

OUTB

FBKB

OUTN

OUTP

FBKA

OUTA

BIAS

TEMP

OUTA

OUTB

CHANNEL A

LOG DETECTOR

ADL5519

CHANNEL B

LOG DETECTOR

Figure 50. Block Diagram

Each measurement channel is a full differential design using

a proprietary, high speed SiGe process that extends high frequency

performance. Figure 51 shows the basic diagram of the Channel A

signal path; its functionality is identical to that of the Channel B

signal path.

INHA

INLA

VSTA

OUTA

CLPA

DET

Figure 51. Single Channel Block Diagram

The maximum input with ±1 dB log conformance error is typically

−5 dBm (re: 50 Ω). The noise spectral density referred to the input

is 1.15 nV/√Hz, which is equivalent to a voltage of 118 μV rms

in a 10.5 GHz bandwidth or a noise power of −66 dBm (re: 50 Ω).

This noise spectral density sets the lower limit of the dynamic

range. However, the low end accuracy of the ADL5519 is enhanced

by specially shaping the demodulating transfer characteristic to

partially compensate for errors due to internal noise. The common

pins provide a quality, low impedance connection to the printed

circuit board (PCB) ground. The package paddle, which is inter-

nally connected to the COMR pins, should also be grounded to

the PCB to reduce thermal impedance from the die to the PCB.

The logarithmic function is approximated in a piecewise fashion

by six cascaded gain stages. For a more comprehensive explana-

tion of the logarithm approximation, refer to the AD8307 data

sheet. The cells have a nominal voltage gain of 9 dB each, with

a 3 dB bandwidth of 10.5 GHz. Using precision biasing, the gain

is stabilized over temperature and supply variations. The overall

dc gain is high because of the cascaded nature of the gain stages.

An offset compensation loop is included to correct for offsets

within the cascaded cells. At the output of each gain stage,

a square-law detector cell is used to rectify the signal.

The RF signal voltages are converted to a fluctuating differential

current, having an average value that increases with signal level.

Along with the six gain stages and detector cells, an additional

detector is included at the input of each measurement channel,

providing a 54 dB dynamic range in total. After the detector

currents are summed and filtered, the following function is

formed at the summing node:

ID × log10(VIN/VINTERCEPT)

(1)

where:

ID is the internally set detector current.

VIN is the input signal voltage.

VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT,

the output voltage would be 0 V, if it were capable of going to 0 V).

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